1/* $NetBSD: nvmm_x86.h,v 1.15 2019/05/11 07:31:56 maxv Exp $ */
2
3/*
4 * Copyright (c) 2018 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Maxime Villard.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _NVMM_X86_H_
33#define _NVMM_X86_H_
34
35/* --------------------------------------------------------------------- */
36
37#ifndef ASM_NVMM
38
39struct nvmm_exit_memory {
40 int prot;
41 gpaddr_t gpa;
42 uint8_t inst_len;
43 uint8_t inst_bytes[15];
44};
45
46enum nvmm_exit_io_type {
47 NVMM_EXIT_IO_IN,
48 NVMM_EXIT_IO_OUT
49};
50
51struct nvmm_exit_io {
52 enum nvmm_exit_io_type type;
53 uint16_t port;
54 int seg;
55 uint8_t address_size;
56 uint8_t operand_size;
57 bool rep;
58 bool str;
59 uint64_t npc;
60};
61
62enum nvmm_exit_msr_type {
63 NVMM_EXIT_MSR_RDMSR,
64 NVMM_EXIT_MSR_WRMSR
65};
66
67struct nvmm_exit_msr {
68 enum nvmm_exit_msr_type type;
69 uint64_t msr;
70 uint64_t val;
71 uint64_t npc;
72};
73
74struct nvmm_exit_insn {
75 uint64_t npc;
76};
77
78struct nvmm_exit_invalid {
79 uint64_t hwcode;
80};
81
82union nvmm_exit_md {
83 struct nvmm_exit_memory mem;
84 struct nvmm_exit_io io;
85 struct nvmm_exit_msr msr;
86 struct nvmm_exit_insn insn;
87 struct nvmm_exit_invalid inv;
88};
89
90#define NVMM_EXIT_MONITOR 0x0000000000001000ULL
91#define NVMM_EXIT_MWAIT 0x0000000000001001ULL
92#define NVMM_EXIT_MWAIT_COND 0x0000000000001002ULL
93
94struct nvmm_cap_md {
95 uint64_t xcr0_mask;
96 uint64_t mxcsr_mask;
97 uint64_t conf_cpuid_maxops;
98 uint64_t rsvd[5];
99};
100
101#endif
102
103/* --------------------------------------------------------------------- */
104
105/* Segments. */
106#define NVMM_X64_SEG_ES 0
107#define NVMM_X64_SEG_CS 1
108#define NVMM_X64_SEG_SS 2
109#define NVMM_X64_SEG_DS 3
110#define NVMM_X64_SEG_FS 4
111#define NVMM_X64_SEG_GS 5
112#define NVMM_X64_SEG_GDT 6
113#define NVMM_X64_SEG_IDT 7
114#define NVMM_X64_SEG_LDT 8
115#define NVMM_X64_SEG_TR 9
116#define NVMM_X64_NSEG 10
117
118/* General Purpose Registers. */
119#define NVMM_X64_GPR_RAX 0
120#define NVMM_X64_GPR_RCX 1
121#define NVMM_X64_GPR_RDX 2
122#define NVMM_X64_GPR_RBX 3
123#define NVMM_X64_GPR_RSP 4
124#define NVMM_X64_GPR_RBP 5
125#define NVMM_X64_GPR_RSI 6
126#define NVMM_X64_GPR_RDI 7
127#define NVMM_X64_GPR_R8 8
128#define NVMM_X64_GPR_R9 9
129#define NVMM_X64_GPR_R10 10
130#define NVMM_X64_GPR_R11 11
131#define NVMM_X64_GPR_R12 12
132#define NVMM_X64_GPR_R13 13
133#define NVMM_X64_GPR_R14 14
134#define NVMM_X64_GPR_R15 15
135#define NVMM_X64_GPR_RIP 16
136#define NVMM_X64_GPR_RFLAGS 17
137#define NVMM_X64_NGPR 18
138
139/* Control Registers. */
140#define NVMM_X64_CR_CR0 0
141#define NVMM_X64_CR_CR2 1
142#define NVMM_X64_CR_CR3 2
143#define NVMM_X64_CR_CR4 3
144#define NVMM_X64_CR_CR8 4
145#define NVMM_X64_CR_XCR0 5
146#define NVMM_X64_NCR 6
147
148/* Debug Registers. */
149#define NVMM_X64_DR_DR0 0
150#define NVMM_X64_DR_DR1 1
151#define NVMM_X64_DR_DR2 2
152#define NVMM_X64_DR_DR3 3
153#define NVMM_X64_DR_DR6 4
154#define NVMM_X64_DR_DR7 5
155#define NVMM_X64_NDR 6
156
157/* MSRs. */
158#define NVMM_X64_MSR_EFER 0
159#define NVMM_X64_MSR_STAR 1
160#define NVMM_X64_MSR_LSTAR 2
161#define NVMM_X64_MSR_CSTAR 3
162#define NVMM_X64_MSR_SFMASK 4
163#define NVMM_X64_MSR_KERNELGSBASE 5
164#define NVMM_X64_MSR_SYSENTER_CS 6
165#define NVMM_X64_MSR_SYSENTER_ESP 7
166#define NVMM_X64_MSR_SYSENTER_EIP 8
167#define NVMM_X64_MSR_PAT 9
168#define NVMM_X64_MSR_TSC 10
169#define NVMM_X64_NMSR 11
170
171#ifndef ASM_NVMM
172
173#include <sys/types.h>
174#include <x86/cpu_extended_state.h>
175
176struct nvmm_x64_state_seg {
177 uint16_t selector;
178 struct { /* hidden */
179 uint16_t type:4;
180 uint16_t s:1;
181 uint16_t dpl:2;
182 uint16_t p:1;
183 uint16_t avl:1;
184 uint16_t l:1;
185 uint16_t def:1;
186 uint16_t g:1;
187 uint16_t rsvd:4;
188 } attrib;
189 uint32_t limit; /* hidden */
190 uint64_t base; /* hidden */
191};
192
193struct nvmm_x64_state_intr {
194 uint64_t int_shadow:1;
195 uint64_t int_window_exiting:1;
196 uint64_t nmi_window_exiting:1;
197 uint64_t evt_pending:1;
198 uint64_t rsvd:60;
199};
200
201/* VM exit state indexes. */
202#define NVMM_X64_EXITSTATE_CR8 0
203#define NVMM_X64_EXITSTATE_RFLAGS 1
204#define NVMM_X64_EXITSTATE_INT_SHADOW 2
205#define NVMM_X64_EXITSTATE_INT_WINDOW_EXIT 3
206#define NVMM_X64_EXITSTATE_NMI_WINDOW_EXIT 4
207#define NVMM_X64_EXITSTATE_EVT_PENDING 5
208
209/* Flags. */
210#define NVMM_X64_STATE_SEGS 0x01
211#define NVMM_X64_STATE_GPRS 0x02
212#define NVMM_X64_STATE_CRS 0x04
213#define NVMM_X64_STATE_DRS 0x08
214#define NVMM_X64_STATE_MSRS 0x10
215#define NVMM_X64_STATE_INTR 0x20
216#define NVMM_X64_STATE_FPU 0x40
217#define NVMM_X64_STATE_ALL \
218 (NVMM_X64_STATE_SEGS | NVMM_X64_STATE_GPRS | NVMM_X64_STATE_CRS | \
219 NVMM_X64_STATE_DRS | NVMM_X64_STATE_MSRS | NVMM_X64_STATE_INTR | \
220 NVMM_X64_STATE_FPU)
221
222struct nvmm_x64_state {
223 struct nvmm_x64_state_seg segs[NVMM_X64_NSEG];
224 uint64_t gprs[NVMM_X64_NGPR];
225 uint64_t crs[NVMM_X64_NCR];
226 uint64_t drs[NVMM_X64_NDR];
227 uint64_t msrs[NVMM_X64_NMSR];
228 struct nvmm_x64_state_intr intr;
229 struct fxsave fpu;
230};
231
232#define nvmm_vcpu_state nvmm_x64_state
233
234#define NVMM_MACH_CONF_X86_CPUID NVMM_MACH_CONF_MD_BEGIN
235#define NVMM_X86_NCONF 1
236
237struct nvmm_mach_conf_x86_cpuid {
238 uint32_t leaf;
239 struct {
240 uint32_t eax;
241 uint32_t ebx;
242 uint32_t ecx;
243 uint32_t edx;
244 } set;
245 struct {
246 uint32_t eax;
247 uint32_t ebx;
248 uint32_t ecx;
249 uint32_t edx;
250 } del;
251};
252
253#ifdef _KERNEL
254struct nvmm_x86_cpuid_mask {
255 uint32_t eax;
256 uint32_t ebx;
257 uint32_t ecx;
258 uint32_t edx;
259};
260extern const struct nvmm_x64_state nvmm_x86_reset_state;
261extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000001;
262extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007;
263extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000001;
264bool nvmm_x86_pat_validate(uint64_t);
265#endif
266
267#endif /* ASM_NVMM */
268
269#endif /* _NVMM_X86_H_ */
270