1/* $NetBSD: pcireg.h,v 1.147 2019/03/01 09:26:00 msaitoh Exp $ */
2
3/*
4 * Copyright (c) 1995, 1996, 1999, 2000
5 * Christopher G. Demetriou. All rights reserved.
6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Charles M. Hannum.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef _DEV_PCI_PCIREG_H_
35#define _DEV_PCI_PCIREG_H_
36
37/*
38 * Standardized PCI configuration information
39 */
40
41/*
42 * Size of each function's configuration space.
43 */
44
45#define PCI_CONF_SIZE 0x100
46#define PCI_EXTCONF_SIZE 0x1000
47
48/*
49 * Device identification register; contains a vendor ID and a device ID.
50 */
51#define PCI_ID_REG 0x00
52
53typedef u_int16_t pci_vendor_id_t;
54typedef u_int16_t pci_product_id_t;
55
56#define PCI_VENDOR_SHIFT 0
57#define PCI_VENDOR_MASK 0xffff
58#define PCI_VENDOR(id) \
59 (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
60
61#define PCI_PRODUCT_SHIFT 16
62#define PCI_PRODUCT_MASK 0xffff
63#define PCI_PRODUCT(id) \
64 (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
65
66#define PCI_ID_CODE(vid,pid) \
67 ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \
68 (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT)) \
69
70/*
71 * Command and status register.
72 */
73#define PCI_COMMAND_STATUS_REG 0x04
74#define PCI_COMMAND_SHIFT 0
75#define PCI_COMMAND_MASK 0xffff
76#define PCI_STATUS_SHIFT 16
77#define PCI_STATUS_MASK 0xffff
78
79#define PCI_COMMAND_STATUS_CODE(cmd,stat) \
80 ((((cmd) & PCI_COMMAND_MASK) << PCI_COMMAND_SHIFT) | \
81 (((stat) & PCI_STATUS_MASK) << PCI_STATUS_SHIFT)) \
82
83#define PCI_COMMAND_IO_ENABLE 0x00000001
84#define PCI_COMMAND_MEM_ENABLE 0x00000002
85#define PCI_COMMAND_MASTER_ENABLE 0x00000004
86#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
87#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
88#define PCI_COMMAND_PALETTE_ENABLE 0x00000020
89#define PCI_COMMAND_PARITY_ENABLE 0x00000040
90#define PCI_COMMAND_STEPPING_ENABLE 0x00000080
91#define PCI_COMMAND_SERR_ENABLE 0x00000100
92#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
93#define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400
94
95#define PCI_STATUS_IMMD_READNESS __BIT(0+16)
96#define PCI_STATUS_INT_STATUS 0x00080000
97#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
98#define PCI_STATUS_66MHZ_SUPPORT 0x00200000
99#define PCI_STATUS_UDF_SUPPORT 0x00400000
100#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000
101#define PCI_STATUS_PARITY_ERROR 0x01000000
102#define PCI_STATUS_DEVSEL_FAST 0x00000000
103#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
104#define PCI_STATUS_DEVSEL_SLOW 0x04000000
105#define PCI_STATUS_DEVSEL_MASK 0x06000000
106#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
107#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
108#define PCI_STATUS_MASTER_ABORT 0x20000000
109#define PCI_STATUS_SPECIAL_ERROR 0x40000000
110#define PCI_STATUS_PARITY_DETECT 0x80000000
111
112/*
113 * PCI Class and Revision Register; defines type and revision of device.
114 */
115#define PCI_CLASS_REG 0x08
116
117typedef u_int8_t pci_class_t;
118typedef u_int8_t pci_subclass_t;
119typedef u_int8_t pci_interface_t;
120typedef u_int8_t pci_revision_t;
121
122#define PCI_CLASS_SHIFT 24
123#define PCI_CLASS_MASK 0xff
124#define PCI_CLASS(cr) \
125 (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
126
127#define PCI_SUBCLASS_SHIFT 16
128#define PCI_SUBCLASS_MASK 0xff
129#define PCI_SUBCLASS(cr) \
130 (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
131
132#define PCI_INTERFACE_SHIFT 8
133#define PCI_INTERFACE_MASK 0xff
134#define PCI_INTERFACE(cr) \
135 (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
136
137#define PCI_REVISION_SHIFT 0
138#define PCI_REVISION_MASK 0xff
139#define PCI_REVISION(cr) \
140 (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
141
142#define PCI_CLASS_CODE(mainclass, subclass, interface) \
143 ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \
144 (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \
145 (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT))
146
147/* base classes */
148#define PCI_CLASS_PREHISTORIC 0x00
149#define PCI_CLASS_MASS_STORAGE 0x01
150#define PCI_CLASS_NETWORK 0x02
151#define PCI_CLASS_DISPLAY 0x03
152#define PCI_CLASS_MULTIMEDIA 0x04
153#define PCI_CLASS_MEMORY 0x05
154#define PCI_CLASS_BRIDGE 0x06
155#define PCI_CLASS_COMMUNICATIONS 0x07
156#define PCI_CLASS_SYSTEM 0x08
157#define PCI_CLASS_INPUT 0x09
158#define PCI_CLASS_DOCK 0x0a
159#define PCI_CLASS_PROCESSOR 0x0b
160#define PCI_CLASS_SERIALBUS 0x0c
161#define PCI_CLASS_WIRELESS 0x0d
162#define PCI_CLASS_I2O 0x0e
163#define PCI_CLASS_SATCOM 0x0f
164#define PCI_CLASS_CRYPTO 0x10
165#define PCI_CLASS_DASP 0x11
166#define PCI_CLASS_ACCEL 0x12
167#define PCI_CLASS_INSTRUMENT 0x13
168#define PCI_CLASS_UNDEFINED 0xff
169
170/* 0x00 prehistoric subclasses */
171#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
172#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
173
174/* 0x01 mass storage subclasses */
175#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
176#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
177#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
178#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
179#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
180#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05
181#define PCI_INTERFACE_ATA_SINGLEDMA 0x20
182#define PCI_INTERFACE_ATA_CHAINEDDMA 0x30
183#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06
184#define PCI_INTERFACE_SATA_VND 0x00
185#define PCI_INTERFACE_SATA_AHCI10 0x01
186#define PCI_INTERFACE_SATA_SSBI 0x02
187#define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07
188#define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08
189#define PCI_INTERFACE_NVM_VND 0x00
190#define PCI_INTERFACE_NVM_NVMHCI10 0x01
191#define PCI_INTERFACE_NVM_NVME 0x02
192#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
193
194/* 0x02 network subclasses */
195#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
196#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
197#define PCI_SUBCLASS_NETWORK_FDDI 0x02
198#define PCI_SUBCLASS_NETWORK_ATM 0x03
199#define PCI_SUBCLASS_NETWORK_ISDN 0x04
200#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05
201#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
202#define PCI_SUBCLASS_NETWORK_INFINIBAND 0x07
203#define PCI_SUBCLASS_NETWORK_MISC 0x80
204
205/* 0x03 display subclasses */
206#define PCI_SUBCLASS_DISPLAY_VGA 0x00
207#define PCI_INTERFACE_VGA_VGA 0x00
208#define PCI_INTERFACE_VGA_8514 0x01
209#define PCI_SUBCLASS_DISPLAY_XGA 0x01
210#define PCI_SUBCLASS_DISPLAY_3D 0x02
211#define PCI_SUBCLASS_DISPLAY_MISC 0x80
212
213/* 0x04 multimedia subclasses */
214#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
215#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
216#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02
217#define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03
218#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
219
220/* 0x05 memory subclasses */
221#define PCI_SUBCLASS_MEMORY_RAM 0x00
222#define PCI_SUBCLASS_MEMORY_FLASH 0x01
223#define PCI_SUBCLASS_MEMORY_MISC 0x80
224
225/* 0x06 bridge subclasses */
226#define PCI_SUBCLASS_BRIDGE_HOST 0x00
227#define PCI_SUBCLASS_BRIDGE_ISA 0x01
228#define PCI_SUBCLASS_BRIDGE_EISA 0x02
229#define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA */
230#define PCI_SUBCLASS_BRIDGE_PCI 0x04
231#define PCI_INTERFACE_BRIDGE_PCI_PCI 0x00
232#define PCI_INTERFACE_BRIDGE_PCI_SUBDEC 0x01
233#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
234#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
235#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
236#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
237 /* bit0 == 0 ? "transparent mode" : "endpoint mode" */
238#define PCI_SUBCLASS_BRIDGE_STPCI 0x09
239#define PCI_INTERFACE_STPCI_PRIMARY 0x40
240#define PCI_INTERFACE_STPCI_SECONDARY 0x80
241#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
242#define PCI_SUBCLASS_BRIDGE_ADVSW 0x0b
243#define PCI_INTERFACE_ADVSW_CUSTOM 0x00
244#define PCI_INTERFACE_ADVSW_ASISIG 0x01
245#define PCI_SUBCLASS_BRIDGE_MISC 0x80
246
247/* 0x07 communications subclasses */
248#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
249#define PCI_INTERFACE_SERIAL_XT 0x00
250#define PCI_INTERFACE_SERIAL_16450 0x01
251#define PCI_INTERFACE_SERIAL_16550 0x02
252#define PCI_INTERFACE_SERIAL_16650 0x03
253#define PCI_INTERFACE_SERIAL_16750 0x04
254#define PCI_INTERFACE_SERIAL_16850 0x05
255#define PCI_INTERFACE_SERIAL_16950 0x06
256#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
257#define PCI_INTERFACE_PARALLEL 0x00
258#define PCI_INTERFACE_PARALLEL_BIDIRECTIONAL 0x01
259#define PCI_INTERFACE_PARALLEL_ECP1X 0x02
260#define PCI_INTERFACE_PARALLEL_IEEE1284_CNTRL 0x03
261#define PCI_INTERFACE_PARALLEL_IEEE1284_TGT 0xfe
262#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02
263#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
264#define PCI_INTERFACE_MODEM 0x00
265#define PCI_INTERFACE_MODEM_HAYES16450 0x01
266#define PCI_INTERFACE_MODEM_HAYES16550 0x02
267#define PCI_INTERFACE_MODEM_HAYES16650 0x03
268#define PCI_INTERFACE_MODEM_HAYES16750 0x04
269#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04
270#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05
271#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
272
273/* 0x08 system subclasses */
274#define PCI_SUBCLASS_SYSTEM_PIC 0x00
275#define PCI_INTERFACE_PIC_8259 0x00
276#define PCI_INTERFACE_PIC_ISA 0x01
277#define PCI_INTERFACE_PIC_EISA 0x02
278#define PCI_INTERFACE_PIC_IOAPIC 0x10
279#define PCI_INTERFACE_PIC_IOXAPIC 0x20
280#define PCI_SUBCLASS_SYSTEM_DMA 0x01
281#define PCI_INTERFACE_DMA_8237 0x00
282#define PCI_INTERFACE_DMA_ISA 0x01
283#define PCI_INTERFACE_DMA_EISA 0x02
284#define PCI_SUBCLASS_SYSTEM_TIMER 0x02
285#define PCI_INTERFACE_TIMER_8254 0x00
286#define PCI_INTERFACE_TIMER_ISA 0x01
287#define PCI_INTERFACE_TIMER_EISA 0x02
288#define PCI_INTERFACE_TIMER_HPET 0x03
289#define PCI_SUBCLASS_SYSTEM_RTC 0x03
290#define PCI_INTERFACE_RTC_GENERIC 0x00
291#define PCI_INTERFACE_RTC_ISA 0x01
292#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04
293#define PCI_SUBCLASS_SYSTEM_SDHC 0x05
294#define PCI_SUBCLASS_SYSTEM_IOMMU 0x06 /* or RCEC in old spec */
295#define PCI_SUBCLASS_SYSTEM_RCEC 0x07
296#define PCI_SUBCLASS_SYSTEM_MISC 0x80
297
298/* 0x09 input subclasses */
299#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
300#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
301#define PCI_SUBCLASS_INPUT_MOUSE 0x02
302#define PCI_SUBCLASS_INPUT_SCANNER 0x03
303#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
304#define PCI_INTERFACE_GAMEPORT_GENERIC 0x00
305#define PCI_INTERFACE_GAMEPORT_LEGACY 0x10
306#define PCI_SUBCLASS_INPUT_MISC 0x80
307
308/* 0x0a dock subclasses */
309#define PCI_SUBCLASS_DOCK_GENERIC 0x00
310#define PCI_SUBCLASS_DOCK_MISC 0x80
311
312/* 0x0b processor subclasses */
313#define PCI_SUBCLASS_PROCESSOR_386 0x00
314#define PCI_SUBCLASS_PROCESSOR_486 0x01
315#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
316#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
317#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
318#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
319#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
320#define PCI_SUBCLASS_PROCESSOR_MISC 0x80
321
322/* 0x0c serial bus subclasses */
323#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
324#define PCI_INTERFACE_IEEE1394_FIREWIRE 0x00
325#define PCI_INTERFACE_IEEE1394_OPENHCI 0x10
326#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01
327#define PCI_SUBCLASS_SERIALBUS_SSA 0x02
328#define PCI_SUBCLASS_SERIALBUS_USB 0x03
329#define PCI_INTERFACE_USB_UHCI 0x00
330#define PCI_INTERFACE_USB_OHCI 0x10
331#define PCI_INTERFACE_USB_EHCI 0x20
332#define PCI_INTERFACE_USB_XHCI 0x30
333#define PCI_INTERFACE_USB_OTHERHC 0x80
334#define PCI_INTERFACE_USB_DEVICE 0xfe
335#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */
336#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05
337#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 /* Deprecated */
338#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07
339#define PCI_INTERFACE_IPMI_SMIC 0x00
340#define PCI_INTERFACE_IPMI_KBD 0x01
341#define PCI_INTERFACE_IPMI_BLOCKXFER 0x02
342#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
343#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
344#define PCI_SUBCLASS_SERIALBUS_MISC 0x80
345
346/* 0x0d wireless subclasses */
347#define PCI_SUBCLASS_WIRELESS_IRDA 0x00
348#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01
349#define PCI_INTERFACE_CONSUMERIR 0x00
350#define PCI_INTERFACE_UWB 0x10
351#define PCI_SUBCLASS_WIRELESS_RF 0x10
352#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11
353#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12
354#define PCI_SUBCLASS_WIRELESS_802_11A 0x20
355#define PCI_SUBCLASS_WIRELESS_802_11B 0x21
356#define PCI_SUBCLASS_WIRELESS_MISC 0x80
357
358/* 0x0e I2O (Intelligent I/O) subclasses */
359#define PCI_SUBCLASS_I2O_STANDARD 0x00
360#define PCI_INTERFACE_I2O_FIFOAT40 0x00
361 /* others for I2O spec */
362#define PCI_SUBCLASS_I2O_MISC 0x80
363
364/* 0x0f satellite communication subclasses */
365/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */
366#define PCI_SUBCLASS_SATCOM_TV 0x01
367#define PCI_SUBCLASS_SATCOM_AUDIO 0x02
368#define PCI_SUBCLASS_SATCOM_VOICE 0x03
369#define PCI_SUBCLASS_SATCOM_DATA 0x04
370#define PCI_SUBCLASS_SATCOM_MISC 0x80
371
372/* 0x10 encryption/decryption subclasses */
373#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00
374#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10
375#define PCI_SUBCLASS_CRYPTO_MISC 0x80
376
377/* 0x11 data acquisition and signal processing subclasses */
378#define PCI_SUBCLASS_DASP_DPIO 0x00
379#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01 /* performance counters */
380#define PCI_SUBCLASS_DASP_SYNC 0x10
381#define PCI_SUBCLASS_DASP_MGMT 0x20
382#define PCI_SUBCLASS_DASP_MISC 0x80
383
384/*
385 * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
386 */
387#define PCI_BHLC_REG 0x0c
388
389#define PCI_BIST_SHIFT 24
390#define PCI_BIST_MASK 0xff
391#define PCI_BIST(bhlcr) \
392 (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
393
394#define PCI_HDRTYPE_SHIFT 16
395#define PCI_HDRTYPE_MASK 0xff
396#define PCI_HDRTYPE(bhlcr) \
397 (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
398
399#define PCI_HDRTYPE_TYPE(bhlcr) \
400 (PCI_HDRTYPE(bhlcr) & 0x7f)
401#define PCI_HDRTYPE_MULTIFN(bhlcr) \
402 ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
403
404#define PCI_LATTIMER_SHIFT 8
405#define PCI_LATTIMER_MASK 0xff
406#define PCI_LATTIMER(bhlcr) \
407 (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
408
409#define PCI_CACHELINE_SHIFT 0
410#define PCI_CACHELINE_MASK 0xff
411#define PCI_CACHELINE(bhlcr) \
412 (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
413
414#define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \
415 ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \
416 (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \
417 (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \
418 (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \
419 (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))
420
421/*
422 * PCI header type
423 */
424#define PCI_HDRTYPE_DEVICE 0 /* PCI/PCIX/Cardbus */
425#define PCI_HDRTYPE_PPB 1 /* PCI/PCIX/Cardbus */
426#define PCI_HDRTYPE_PCB 2 /* PCI/PCIX/Cardbus */
427#define PCI_HDRTYPE_EP 0 /* PCI Express */
428#define PCI_HDRTYPE_RC 1 /* PCI Express */
429
430
431/*
432 * Mapping registers
433 */
434#define PCI_MAPREG_START 0x10
435#define PCI_MAPREG_END 0x28
436#define PCI_MAPREG_ROM 0x30
437#define PCI_MAPREG_PPB_END 0x18
438#define PCI_MAPREG_PCB_END 0x14
439
440#define PCI_BAR0 0x10
441#define PCI_BAR1 0x14
442#define PCI_BAR2 0x18
443#define PCI_BAR3 0x1C
444#define PCI_BAR4 0x20
445#define PCI_BAR5 0x24
446
447#define PCI_BAR(__n) (PCI_MAPREG_START + 4 * (__n))
448
449#define PCI_MAPREG_TYPE(mr) \
450 ((mr) & PCI_MAPREG_TYPE_MASK)
451#define PCI_MAPREG_TYPE_MASK 0x00000001
452
453#define PCI_MAPREG_TYPE_MEM 0x00000000
454#define PCI_MAPREG_TYPE_ROM 0x00000000
455#define PCI_MAPREG_TYPE_IO 0x00000001
456#define PCI_MAPREG_ROM_ENABLE 0x00000001
457
458#define PCI_MAPREG_MEM_TYPE(mr) \
459 ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
460#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
461
462#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
463#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
464#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
465
466#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \
467 (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
468#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
469
470#define PCI_MAPREG_MEM_ADDR(mr) \
471 ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
472#define PCI_MAPREG_MEM_SIZE(mr) \
473 (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
474#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
475
476#define PCI_MAPREG_MEM64_ADDR(mr) \
477 ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
478#define PCI_MAPREG_MEM64_SIZE(mr) \
479 (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
480#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL
481
482#define PCI_MAPREG_IO_ADDR(mr) \
483 ((mr) & PCI_MAPREG_IO_ADDR_MASK)
484#define PCI_MAPREG_IO_SIZE(mr) \
485 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
486#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc
487
488#define PCI_MAPREG_ROM_ADDR(mr) \
489 ((mr) & PCI_MAPREG_ROM_ADDR_MASK)
490#define PCI_MAPREG_ROM_VALID_STAT __BITS(3, 1) /* Validation Status */
491#define PCI_MAPREG_ROM_VSTAT_NOTSUPP 0x0 /* Validation not supported */
492#define PCI_MAPREG_ROM_VSTAT_INPROG 0x1 /* Validation in Progress */
493#define PCI_MAPREG_ROM_VSTAT_VPASS 0x2 /* Valid contnt, trust test nperf*/
494#define PCI_MAPREG_ROM_VSTAT_VPASSTRUST 0x3 /* Valid and trusted contents */
495#define PCI_MAPREG_ROM_VSTAT_VFAIL 0x4 /* Invaild contents */
496#define PCI_MAPREG_ROM_VSTAT_VFAILUNTRUST 0x5 /* Vaild but untrusted contents*/
497#define PCI_MAPREG_ROM_VSTAT_WPASS 0x6 /* VPASS + warning */
498#define PCI_MAPREG_ROM_VSTAT_WPASSTRUST 0x7 /* VPASSTRUST + warning */
499#define PCI_MAPREG_ROM_VALID_DETAIL __BITS(7, 4) /* Validation Details */
500#define PCI_MAPREG_ROM_ADDR_MASK __BITS(31, 11)
501
502#define PCI_MAPREG_SIZE_TO_MASK(size) \
503 (-(size))
504
505#define PCI_MAPREG_NUM(offset) \
506 (((unsigned)(offset)-PCI_MAPREG_START)/4)
507
508
509/*
510 * Cardbus CIS pointer (PCI rev. 2.1)
511 */
512#define PCI_CARDBUS_CIS_REG 0x28
513
514/*
515 * Subsystem identification register; contains a vendor ID and a device ID.
516 * Types/macros for PCI_ID_REG apply.
517 * (PCI rev. 2.1)
518 */
519#define PCI_SUBSYS_ID_REG 0x2c
520
521#define PCI_SUBSYS_VENDOR_MASK __BITS(15, 0)
522#define PCI_SUBSYS_ID_MASK __BITS(31, 16)
523
524#define PCI_SUBSYS_VENDOR(__subsys_id) \
525 __SHIFTOUT(__subsys_id, PCI_SUBSYS_VENDOR_MASK)
526
527#define PCI_SUBSYS_ID(__subsys_id) \
528 __SHIFTOUT(__subsys_id, PCI_SUBSYS_ID_MASK)
529
530/*
531 * Capabilities link list (PCI rev. 2.2)
532 */
533#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
534#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
535#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
536#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
537#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
538
539#define PCI_CAP_RESERVED0 0x00
540#define PCI_CAP_PWRMGMT 0x01
541#define PCI_CAP_AGP 0x02
542#define PCI_CAP_VPD 0x03
543#define PCI_CAP_SLOTID 0x04
544#define PCI_CAP_MSI 0x05
545#define PCI_CAP_CPCI_HOTSWAP 0x06
546#define PCI_CAP_PCIX 0x07
547#define PCI_CAP_LDT 0x08 /* HyperTransport */
548#define PCI_CAP_VENDSPEC 0x09
549#define PCI_CAP_DEBUGPORT 0x0a
550#define PCI_CAP_CPCI_RSRCCTL 0x0b
551#define PCI_CAP_HOTPLUG 0x0c /* Standard Hot-Plug Controller(SHPC)*/
552#define PCI_CAP_SUBVENDOR 0x0d
553#define PCI_CAP_AGP8 0x0e
554#define PCI_CAP_SECURE 0x0f
555#define PCI_CAP_PCIEXPRESS 0x10
556#define PCI_CAP_MSIX 0x11
557#define PCI_CAP_SATA 0x12
558#define PCI_CAP_PCIAF 0x13
559#define PCI_CAP_EA 0x14 /* Enhanced Allocation (EA) */
560#define PCI_CAP_FPB 0x15 /* Flattening Portal Bridge (FPB) */
561
562/*
563 * Capability ID: 0x01
564 * Power Management Capability; access via capability pointer.
565 */
566
567/* Power Management Capability Register */
568#define PCI_PMCR 0x02
569#define PCI_PMCR_SHIFT 16
570#define PCI_PMCR_VERSION_MASK 0x0007
571#define PCI_PMCR_VERSION_10 0x0001
572#define PCI_PMCR_VERSION_11 0x0002
573#define PCI_PMCR_VERSION_12 0x0003
574#define PCI_PMCR_PME_CLOCK 0x0008
575#define PCI_PMCR_DSI 0x0020
576#define PCI_PMCR_AUXCUR_MASK 0x01c0
577#define PCI_PMCR_AUXCUR_0 0x0000
578#define PCI_PMCR_AUXCUR_55 0x0040
579#define PCI_PMCR_AUXCUR_100 0x0080
580#define PCI_PMCR_AUXCUR_160 0x00c0
581#define PCI_PMCR_AUXCUR_220 0x0100
582#define PCI_PMCR_AUXCUR_270 0x0140
583#define PCI_PMCR_AUXCUR_320 0x0180
584#define PCI_PMCR_AUXCUR_375 0x01c0
585#define PCI_PMCR_D1SUPP 0x0200
586#define PCI_PMCR_D2SUPP 0x0400
587#define PCI_PMCR_PME_D0 0x0800
588#define PCI_PMCR_PME_D1 0x1000
589#define PCI_PMCR_PME_D2 0x2000
590#define PCI_PMCR_PME_D3HOT 0x4000
591#define PCI_PMCR_PME_D3COLD 0x8000
592/*
593 * Power Management Control Status Register, Bridge Support Extensions Register
594 * and Data Register.
595 */
596#define PCI_PMCSR 0x04
597#define PCI_PMCSR_STATE_MASK 0x00000003
598#define PCI_PMCSR_STATE_D0 0x00000000
599#define PCI_PMCSR_STATE_D1 0x00000001
600#define PCI_PMCSR_STATE_D2 0x00000002
601#define PCI_PMCSR_STATE_D3 0x00000003
602#define PCI_PMCSR_NO_SOFTRST 0x00000008
603#define PCI_PMCSR_PME_EN 0x00000100
604#define PCI_PMCSR_DATASEL_MASK 0x00001e00
605#define PCI_PMCSR_DATASCL_MASK 0x00006000
606#define PCI_PMCSR_PME_STS 0x00008000
607#define PCI_PMCSR_B2B3_SUPPORT 0x00400000
608#define PCI_PMCSR_BPCC_EN 0x00800000
609#define PCI_PMCSR_DATA 0xff000000
610
611
612/*
613 * Capability ID: 0x02
614 * AGP
615 */
616#define PCI_CAP_AGP_MAJOR(cr) (((cr) >> 20) & 0xf)
617#define PCI_CAP_AGP_MINOR(cr) (((cr) >> 16) & 0xf)
618#define PCI_AGP_STATUS 0x04
619#define PCI_AGP_COMMAND 0x08
620/* Definitions for STATUS and COMMAND register bits */
621#define AGP_MODE_RQ __BITS(31, 24)
622#define AGP_MODE_ARQSZ __BITS(15, 13)
623#define AGP_MODE_CAL __BITS(12, 10)
624#define AGP_MODE_SBA __BIT(9)
625#define AGP_MODE_AGP __BIT(8)
626#define AGP_MODE_HTRANS __BIT(6)
627#define AGP_MODE_4G __BIT(5)
628#define AGP_MODE_FW __BIT(4)
629#define AGP_MODE_MODE_3 __BIT(3)
630#define AGP_MODE_RATE __BITS(2, 0)
631#define AGP_MODE_V2_RATE_1x 0x1
632#define AGP_MODE_V2_RATE_2x 0x2
633#define AGP_MODE_V2_RATE_4x 0x4
634#define AGP_MODE_V3_RATE_4x 0x1
635#define AGP_MODE_V3_RATE_8x 0x2
636#define AGP_MODE_V3_RATE_RSVD 0x4
637
638
639/*
640 * Capability ID: 0x03
641 * Vital Product Data; access via capability pointer (PCI rev 2.2).
642 */
643#define PCI_VPD_ADDRESS_MASK 0x7fff
644#define PCI_VPD_ADDRESS_SHIFT 16
645#define PCI_VPD_ADDRESS(ofs) \
646 (((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT)
647#define PCI_VPD_DATAREG(ofs) ((ofs) + 4)
648#define PCI_VPD_OPFLAG 0x80000000
649
650/*
651 * Capability ID: 0x04
652 * Slot ID
653 */
654
655/*
656 * Capability ID: 0x05
657 * MSI
658 */
659
660#define PCI_MSI_CTL 0x0 /* Message Control Register offset */
661#define PCI_MSI_MADDR 0x4 /* Message Address Register (least
662 * significant bits) offset
663 */
664#define PCI_MSI_MADDR64_LO 0x4 /* 64-bit Message Address Register
665 * (least significant bits) offset
666 */
667#define PCI_MSI_MADDR64_HI 0x8 /* 64-bit Message Address Register
668 * (most significant bits) offset
669 */
670#define PCI_MSI_MDATA 0x8 /* Message Data Register offset */
671#define PCI_MSI_MDATA64 0xc /* 64-bit Message Data Register
672 * offset
673 */
674
675#define PCI_MSI_MASK 0x0c /* Vector Mask register */
676#define PCI_MSI_MASK64 0x10 /* 64-bit Vector Mask register */
677
678#define PCI_MSI_PENDING 0x10 /* Vector Pending register */
679#define PCI_MSI_PENDING64 0x14 /* 64-bit Vector Pending register */
680
681#define PCI_MSI_CTL_MASK __BITS(31, 16)
682#define PCI_MSI_CTL_EXTMDATA_EN __SHIFTIN(__BIT(10), PCI_MSI_CTL_MASK)
683#define PCI_MSI_CTL_EXTMDATA_CAP __SHIFTIN(__BIT(9), PCI_MSI_CTL_MASK)
684#define PCI_MSI_CTL_PERVEC_MASK __SHIFTIN(__BIT(8), PCI_MSI_CTL_MASK)
685#define PCI_MSI_CTL_64BIT_ADDR __SHIFTIN(__BIT(7), PCI_MSI_CTL_MASK)
686#define PCI_MSI_CTL_MME_MASK __SHIFTIN(__BITS(6, 4), PCI_MSI_CTL_MASK)
687#define PCI_MSI_CTL_MME(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MME_MASK)
688#define PCI_MSI_CTL_MMC_MASK __SHIFTIN(__BITS(3, 1), PCI_MSI_CTL_MASK)
689#define PCI_MSI_CTL_MMC(reg) __SHIFTOUT(reg, PCI_MSI_CTL_MMC_MASK)
690#define PCI_MSI_CTL_MSI_ENABLE __SHIFTIN(__BIT(0), PCI_MSI_CTL_MASK)
691
692/*
693 * MSI Message Address is at offset 4.
694 * MSI Message Upper Address (if 64bit) is at offset 8.
695 * MSI Message data is at offset 8 or 12 and is lower 16 bits.
696 * MSI Extended Message data is at offset 8 or 12 and is upper 16 bits.
697 * MSI Mask Bits (32 bit field)
698 * MSI Pending Bits (32 bit field)
699 */
700
701 /* Max number of MSI vectors. See PCI-SIG specification. */
702#define PCI_MSI_MAX_VECTORS 32
703
704/*
705 * Capability ID: 0x07
706 * PCI-X capability.
707 *
708 * PCI-X capability register has two different layouts. One is for bridge
709 * function. Another is for non-bridge functions.
710 */
711
712
713/* For non-bridge functions */
714
715/*
716 * Command. 16 bits at offset 2 (e.g. upper 16 bits of the first 32-bit
717 * word at the capability; the lower 16 bits are the capability ID and
718 * next capability pointer).
719 *
720 * Since we always read PCI config space in 32-bit words, we define these
721 * as 32-bit values, offset and shifted appropriately. Make sure you perform
722 * the appropriate R/M/W cycles!
723 */
724#define PCIX_CMD 0x00
725#define PCIX_CMD_PERR_RECOVER 0x00010000
726#define PCIX_CMD_RELAXED_ORDER 0x00020000
727#define PCIX_CMD_BYTECNT_MASK 0x000c0000
728#define PCIX_CMD_BYTECNT_SHIFT 18
729#define PCIX_CMD_BYTECNT(reg) \
730 (512 << (((reg) & PCIX_CMD_BYTECNT_MASK) >> PCIX_CMD_BYTECNT_SHIFT))
731#define PCIX_CMD_BCNT_512 0x00000000
732#define PCIX_CMD_BCNT_1024 0x00040000
733#define PCIX_CMD_BCNT_2048 0x00080000
734#define PCIX_CMD_BCNT_4096 0x000c0000
735#define PCIX_CMD_SPLTRANS_MASK 0x00700000
736#define PCIX_CMD_SPLTRANS_SHIFT 20
737#define PCIX_CMD_SPLTRANS_1 0x00000000
738#define PCIX_CMD_SPLTRANS_2 0x00100000
739#define PCIX_CMD_SPLTRANS_3 0x00200000
740#define PCIX_CMD_SPLTRANS_4 0x00300000
741#define PCIX_CMD_SPLTRANS_8 0x00400000
742#define PCIX_CMD_SPLTRANS_12 0x00500000
743#define PCIX_CMD_SPLTRANS_16 0x00600000
744#define PCIX_CMD_SPLTRANS_32 0x00700000
745
746/*
747 * Status. 32 bits at offset 4.
748 */
749#define PCIX_STATUS 0x04
750#define PCIX_STATUS_FN_MASK 0x00000007
751#define PCIX_STATUS_DEV_MASK 0x000000f8
752#define PCIX_STATUS_DEV_SHIFT 3
753#define PCIX_STATUS_BUS_MASK 0x0000ff00
754#define PCIX_STATUS_BUS_SHIFT 8
755#define PCIX_STATUS_FN(val) ((val) & PCIX_STATUS_FN_MASK)
756#define PCIX_STATUS_DEV(val) \
757 (((val) & PCIX_STATUS_DEV_MASK) >> PCIX_STATUS_DEV_SHIFT)
758#define PCIX_STATUS_BUS(val) \
759 (((val) & PCIX_STATUS_BUS_MASK) >> PCIX_STATUS_BUS_SHIFT)
760#define PCIX_STATUS_64BIT 0x00010000 /* 64bit device */
761#define PCIX_STATUS_133 0x00020000 /* 133MHz capable */
762#define PCIX_STATUS_SPLDISC 0x00040000 /* Split completion discarded*/
763#define PCIX_STATUS_SPLUNEX 0x00080000 /* Unexpected split complet. */
764#define PCIX_STATUS_DEVCPLX 0x00100000 /* Device Complexity */
765#define PCIX_STATUS_MAXB_MASK 0x00600000 /* MAX memory read Byte count*/
766#define PCIX_STATUS_MAXB_SHIFT 21
767#define PCIX_STATUS_MAXB_512 0x00000000
768#define PCIX_STATUS_MAXB_1024 0x00200000
769#define PCIX_STATUS_MAXB_2048 0x00400000
770#define PCIX_STATUS_MAXB_4096 0x00600000
771#define PCIX_STATUS_MAXST_MASK 0x03800000 /* MAX outstand. Split Trans.*/
772#define PCIX_STATUS_MAXST_SHIFT 23
773#define PCIX_STATUS_MAXST_1 0x00000000
774#define PCIX_STATUS_MAXST_2 0x00800000
775#define PCIX_STATUS_MAXST_3 0x01000000
776#define PCIX_STATUS_MAXST_4 0x01800000
777#define PCIX_STATUS_MAXST_8 0x02000000
778#define PCIX_STATUS_MAXST_12 0x02800000
779#define PCIX_STATUS_MAXST_16 0x03000000
780#define PCIX_STATUS_MAXST_32 0x03800000
781#define PCIX_STATUS_MAXRS_MASK 0x1c000000 /* MAX cumulative Read Size */
782#define PCIX_STATUS_MAXRS_SHIFT 26
783#define PCIX_STATUS_MAXRS_1K 0x00000000
784#define PCIX_STATUS_MAXRS_2K 0x04000000
785#define PCIX_STATUS_MAXRS_4K 0x08000000
786#define PCIX_STATUS_MAXRS_8K 0x0c000000
787#define PCIX_STATUS_MAXRS_16K 0x10000000
788#define PCIX_STATUS_MAXRS_32K 0x14000000
789#define PCIX_STATUS_MAXRS_64K 0x18000000
790#define PCIX_STATUS_MAXRS_128K 0x1c000000
791#define PCIX_STATUS_SCERR 0x20000000 /* rcv. Split Completion ERR.*/
792#define PCIX_STATUS_266 0x40000000 /* 266MHz capable */
793#define PCIX_STATUS_533 0x80000000 /* 533MHz capable */
794
795/* For bridge function */
796
797#define PCIX_BRIDGE_2ND_STATUS 0x00
798#define PCIX_BRIDGE_ST_64BIT 0x00010000 /* Same as PCIX_STATUS (nonb)*/
799#define PCIX_BRIDGE_ST_133 0x00020000 /* Same as PCIX_STATUS (nonb)*/
800#define PCIX_BRIDGE_ST_SPLDISC 0x00040000 /* Same as PCIX_STATUS (nonb)*/
801#define PCIX_BRIDGE_ST_SPLUNEX 0x00080000 /* Same as PCIX_STATUS (nonb)*/
802#define PCIX_BRIDGE_ST_SPLOVRN 0x00100000 /* Split completion overrun */
803#define PCIX_BRIDGE_ST_SPLRQDL 0x00200000 /* Split request delayed */
804#define PCIX_BRIDGE_2NDST_CLKF 0x03c00000 /* Secondary clock frequency */
805#define PCIX_BRIDGE_2NDST_CLKF_SHIFT 22
806#define PCIX_BRIDGE_2NDST_VER_MASK 0x30000000 /* Version */
807#define PCIX_BRIDGE_2NDST_VER_SHIFT 28
808#define PCIX_BRIDGE_ST_266 0x40000000 /* Same as PCIX_STATUS (nonb)*/
809#define PCIX_BRIDGE_ST_533 0x80000000 /* Same as PCIX_STATUS (nonb)*/
810
811#define PCIX_BRIDGE_PRI_STATUS 0x04
812/* Bit 0 to 15 are the same as PCIX_STATUS */
813/* Bit 16 to 21 are the same as PCIX_BRIDGE_2ND_STATUS */
814/* Bit 30 and 31 are the same as PCIX_BRIDGE_2ND_STATUS */
815
816#define PCIX_BRIDGE_UP_STCR 0x08 /* Upstream Split Transaction Control */
817#define PCIX_BRIDGE_DOWN_STCR 0x0c /* Downstream Split Transaction Control */
818/* The layouts of above two registers are the same */
819#define PCIX_BRIDGE_STCAP 0x0000ffff /* Sp. Tr. Capacity */
820#define PCIX_BRIDGE_STCLIM 0xffff0000 /* Sp. Tr. Commitment Limit */
821#define PCIX_BRIDGE_STCLIM_SHIFT 16
822
823/*
824 * Capability ID: 0x08
825 * HyperTransport
826 */
827
828#define PCI_HT_CMD 0x00 /* Capability List & Command Register */
829#define PCI_HT_CMD_MASK __BITS(31, 16)
830#define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \
831 (((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f))
832#define PCI_HT_CAPMASK __BITS(31, 27)
833#define PCI_HT_CAP_SLAVE 0b00000 /* 000xx */
834#define PCI_HT_CAP_HOST 0b00100 /* 001xx */
835#define PCI_HT_CAP_SWITCH 0b01000
836#define PCI_HT_CAP_INTERRUPT 0b10000
837#define PCI_HT_CAP_REVID 0b10001
838#define PCI_HT_CAP_UNITID_CLUMP 0b10010
839#define PCI_HT_CAP_EXTCNFSPACE 0b10011
840#define PCI_HT_CAP_ADDRMAP 0b10100
841#define PCI_HT_CAP_MSIMAP 0b10101
842#define PCI_HT_CAP_DIRECTROUTE 0b10110
843#define PCI_HT_CAP_VCSET 0b10111
844#define PCI_HT_CAP_RETRYMODE 0b11000
845#define PCI_HT_CAP_X86ENCODE 0b11001
846#define PCI_HT_CAP_GEN3 0b11010
847#define PCI_HT_CAP_FLE 0b11011
848#define PCI_HT_CAP_PM 0b11100
849#define PCI_HT_CAP_HIGHNODECNT 0b11101
850
851/*
852 * HT Cap ID: 0b10101
853 * MSI Mapping
854 */
855
856/* Command register bits (31-16)*/
857#define PCI_HT_MSI_ENABLED __BIT(16)
858#define PCI_HT_MSI_FIXED __BIT(17)
859
860#define PCI_HT_MSI_ADDR_LO 0x04 /* Address register (low) */
861#define PCI_HT_MSI_ADDR_LO_MASK __BITS(31, 20)
862#define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL
863#define PCI_HT_MSI_ADDR_HI 0x08 /* Address Register (high) */
864
865/*
866 * Capability ID: 0x09
867 * Vendor Specific
868 */
869#define PCI_VENDORSPECIFIC 0x02
870#define PCI_VENDORSPECIFIC_SHIFT 16
871
872/*
873 * Capability ID: 0x0a
874 * Debug Port
875 */
876#define PCI_DEBUG_BASER 0x00 /* Debug Base Register */
877#define PCI_DEBUG_BASER_SHIFT 16
878#define PCI_DEBUG_PORTOFF_SHIFT 16
879#define PCI_DEBUG_PORTOFF_MASK 0x1fff0000 /* Debug port offset */
880#define PCI_DEBUG_BARNUM_SHIFT 29
881#define PCI_DEBUG_BARNUM_MASK 0xe0000000 /* BAR number */
882
883/*
884 * Capability ID: 0x0b
885 * Compact PCI
886 */
887
888/*
889 * Capability ID: 0x0c
890 * Hotplug
891 */
892
893/*
894 * Capability ID: 0x0d
895 * Subsystem
896 */
897#define PCI_CAP_SUBSYS_ID 0x04
898/* bit field layout is the same as PCI_SUBSYS_ID_REG's one */
899
900/*
901 * Capability ID: 0x0e
902 * AGP8
903 */
904
905/*
906 * Capability ID: 0x0f
907 * Secure Device
908 *
909 * Reference: AMD I/O Virtualization Technology(IOMMU) Specification (#48882)
910 * Revision 3.00.
911 */
912#define PCI_SECURE_CAP 0x00 /* Capability Header */
913#define PCI_SECURE_CAP_TYPE __BITS(18, 16) /* Capability block type */
914#define PCI_SECURE_CAP_TYPE_IOMMU 0x3 /* IOMMU Cap */
915#define PCI_SECURE_CAP_REV __BITS(23, 19) /* Capability revision */
916#define PCI_SECURE_CAP_REV_IOMMU 0x01 /* IOMMU interface */
917/* For IOMMU only */
918#define PCI_SECURE_CAP_IOTLBSUP __BIT(24) /* IOTLB */
919#define PCI_SECURE_CAP_HTTUNNEL __BIT(25) /* HT tunnel translation */
920#define PCI_SECURE_CAP_NPCACHE __BIT(26) /* Not present table entries cahced*/
921#define PCI_SECURE_CAP_EFRSUP __BIT(27) /* IOMMU Ext-Feature Reg */
922#define PCI_SECURE_CAP_EXT __BIT(28) /* IOMMU Misc Info Reg 1 */
923#define PCI_SECURE_IOMMU_BAL 0x04 /* Base Address Low */
924#define PCI_SECURE_IOMMU_BAL_EN __BIT(0) /* Enable */
925#define PCI_SECURE_IOMMU_BAL_L __BITS(18, 14) /* Base Addr [18:14] */
926#define PCI_SECURE_IOMMU_BAL_H __BITS(31, 19) /* Base Addr [31:19] */
927#define PCI_SECURE_IOMMU_BAH 0x08 /* Base Address High */
928#define PCI_SECURE_IOMMU_RANGE 0x0c /* IOMMU Range */
929#define PCI_SECURE_IOMMU_RANGE_UNITID __BITS(4, 0) /* HT UnitID */
930#define PCI_SECURE_IOMMU_RANGE_RNGVALID __BIT(7) /* Range valid */
931#define PCI_SECURE_IOMMU_RANGE_BUSNUM __BITS(15, 8) /* bus number */
932#define PCI_SECURE_IOMMU_RANGE_FIRSTDEV __BITS(23, 16) /* First device */
933#define PCI_SECURE_IOMMU_RANGE_LASTDEV __BITS(31, 24) /* Last device */
934#define PCI_SECURE_IOMMU_MISC0 0x10 /* IOMMU Miscellaneous Information 0 */
935#define PCI_SECURE_IOMMU_MISC0_MSINUM __BITS(4, 0) /* MSI Message number */
936#define PCI_SECURE_IOMMU_MISC0_GVASIZE __BITS(7, 5) /* Guest Virtual Adr siz */
937#define PCI_SECURE_IOMMU_MISC0_GVASIZE_48B 0x2 /* 48bits */
938#define PCI_SECURE_IOMMU_MISC0_PASIZE __BITS(14, 8) /* Physical Address siz */
939#define PCI_SECURE_IOMMU_MISC0_VASIZE __BITS(21, 15)/* Virtual Address size */
940#define PCI_SECURE_IOMMU_MISC0_ATSRESV __BIT(22) /* ATS resp addr range rsvd */
941#define PCI_SECURE_IOMMU_MISC0_MISNPPR __BITS(31, 27)/* Periph Pg Rq MSI Msgn*/
942#define PCI_SECURE_IOMMU_MISC1 0x14 /* IOMMU Miscellaneous Information 1 */
943#define PCI_SECURE_IOMMU_MISC1_MSINUM __BITS(4, 0) /* MSI Messsage number(GA)*/
944
945/*
946 * Capability ID: 0x10
947 * PCI Express; access via capability pointer.
948 */
949#define PCIE_XCAP 0x00 /* Capability List & Capabilities Register */
950#define PCIE_XCAP_MASK __BITS(31, 16)
951/* Capability Version */
952#define PCIE_XCAP_VER_MASK __SHIFTIN(__BITS(3, 0), PCIE_XCAP_MASK)
953#define PCIE_XCAP_VER(x) __SHIFTOUT((x), PCIE_XCAP_VER_MASK)
954#define PCIE_XCAP_VER_1 1
955#define PCIE_XCAP_VER_2 2
956#define PCIE_XCAP_TYPE_MASK __SHIFTIN(__BITS(7, 4), PCIE_XCAP_MASK)
957#define PCIE_XCAP_TYPE(x) __SHIFTOUT((x), PCIE_XCAP_TYPE_MASK)
958#define PCIE_XCAP_TYPE_PCIE_DEV 0x0
959#define PCIE_XCAP_TYPE_PCI_DEV 0x1
960#define PCIE_XCAP_TYPE_ROOT 0x4
961#define PCIE_XCAP_TYPE_UP 0x5
962#define PCIE_XCAP_TYPE_DOWN 0x6
963#define PCIE_XCAP_TYPE_PCIE2PCI 0x7
964#define PCIE_XCAP_TYPE_PCI2PCIE 0x8
965#define PCIE_XCAP_TYPE_ROOT_INTEP 0x9
966#define PCIE_XCAP_TYPE_ROOT_EVNTC 0xa
967#define PCIE_XCAP_SI __SHIFTIN(__BIT(8), PCIE_XCAP_MASK) /* Slot Implemented */
968#define PCIE_XCAP_IRQ __SHIFTIN(__BITS(13, 9), PCIE_XCAP_MASK)
969#define PCIE_DCAP 0x04 /* Device Capabilities Register */
970#define PCIE_DCAP_MAX_PAYLOAD __BITS(2, 0) /* Max Payload Size Supported */
971#define PCIE_DCAP_PHANTOM_FUNCS __BITS(4, 3) /* Phantom Functions Supported*/
972#define PCIE_DCAP_EXT_TAG_FIELD __BIT(5) /* Extended Tag Field Support */
973#define PCIE_DCAP_L0S_LATENCY __BITS(8, 6) /* Endpoint L0 Accptbl Latency*/
974#define PCIE_DCAP_L1_LATENCY __BITS(11, 9) /* Endpoint L1 Accptbl Latency*/
975#define PCIE_DCAP_ATTN_BUTTON __BIT(12) /* Attention Indicator Button */
976#define PCIE_DCAP_ATTN_IND __BIT(13) /* Attention Indicator Present*/
977#define PCIE_DCAP_PWR_IND __BIT(14) /* Power Indicator Present */
978#define PCIE_DCAP_ROLE_ERR_RPT __BIT(15) /* Role-Based Error Reporting */
979#define PCIE_DCAP_SLOT_PWR_LIM_VAL __BITS(25, 18) /* Cap. Slot PWR Limit Val */
980#define PCIE_DCAP_SLOT_PWR_LIM_SCALE __BITS(27, 26) /* Cap. SlotPWRLimit Scl */
981#define PCIE_DCAP_FLR __BIT(28) /* Function-Level Reset Cap. */
982#define PCIE_DCSR 0x08 /* Device Control & Status Register */
983#define PCIE_DCSR_ENA_COR_ERR __BIT(0) /* Correctable Error Report En*/
984#define PCIE_DCSR_ENA_NFER __BIT(1) /* Non-Fatal Error Report En. */
985#define PCIE_DCSR_ENA_FER __BIT(2) /* Fatal Error Reporting Enabl*/
986#define PCIE_DCSR_ENA_URR __BIT(3) /* Unsupported Request Rpt En */
987#define PCIE_DCSR_ENA_RELAX_ORD __BIT(4) /* Enable Relaxed Ordering */
988#define PCIE_DCSR_MAX_PAYLOAD __BITS(7, 5) /* Max Payload Size */
989#define PCIE_DCSR_EXT_TAG_FIELD __BIT(8) /* Extended Tag Field Enable */
990#define PCIE_DCSR_PHANTOM_FUNCS __BIT(9) /* Phantom Functions Enable */
991#define PCIE_DCSR_AUX_POWER_PM __BIT(10) /* Aux Power PM Enable */
992#define PCIE_DCSR_ENA_NO_SNOOP __BIT(11) /* Enable No Snoop */
993#define PCIE_DCSR_MAX_READ_REQ __BITS(14, 12) /* Max Read Request Size */
994#define PCIE_DCSR_BRDG_CFG_RETRY __BIT(15) /* Bridge Config Retry Enable */
995#define PCIE_DCSR_INITIATE_FLR __BIT(15) /* Initiate Function-Level Rst*/
996#define PCIE_DCSR_CED __BIT(0 + 16) /* Correctable Error Detected */
997#define PCIE_DCSR_NFED __BIT(1 + 16) /* Non-Fatal Error Detected */
998#define PCIE_DCSR_FED __BIT(2 + 16) /* Fatal Error Detected */
999#define PCIE_DCSR_URD __BIT(3 + 16) /* Unsupported Req. Detected */
1000#define PCIE_DCSR_AUX_PWR __BIT(4 + 16) /* Aux Power Detected */
1001#define PCIE_DCSR_TRANSACTION_PND __BIT(5 + 16) /* Transaction Pending */
1002#define PCIE_DCSR_EMGPWRREDD __BIT(6 + 16) /* Emg. Pwr. Reduct. Detected */
1003#define PCIE_LCAP 0x0c /* Link Capabilities Register */
1004#define PCIE_LCAP_MAX_SPEED __BITS(3, 0) /* Max Link Speed */
1005#define PCIE_LCAP_MAX_WIDTH __BITS(9, 4) /* Maximum Link Width */
1006#define PCIE_LCAP_ASPM __BITS(11, 10) /* Active State Link PM Supp. */
1007#define PCIE_LCAP_L0S_EXIT __BITS(14, 12) /* L0s Exit Latency */
1008#define PCIE_LCAP_L1_EXIT __BITS(17, 15) /* L1 Exit Latency */
1009#define PCIE_LCAP_CLOCK_PM __BIT(18) /* Clock Power Management */
1010#define PCIE_LCAP_SURPRISE_DOWN __BIT(19) /* Surprise Down Err Rpt Cap. */
1011#define PCIE_LCAP_DL_ACTIVE __BIT(20) /* Data Link Layer Link Active*/
1012#define PCIE_LCAP_LINK_BW_NOTIFY __BIT(21) /* Link BW Notification Capabl*/
1013#define PCIE_LCAP_ASPM_COMPLIANCE __BIT(22) /* ASPM Optionally Compliance */
1014#define PCIE_LCAP_PORT __BITS(31, 24) /* Port Number */
1015#define PCIE_LCSR 0x10 /* Link Control & Status Register */
1016#define PCIE_LCSR_ASPM_L0S __BIT(0) /* Active State PM Control L0s*/
1017#define PCIE_LCSR_ASPM_L1 __BIT(1) /* Active State PM Control L1 */
1018#define PCIE_LCSR_RCB __BIT(3) /* Read Completion Boundry Ctl*/
1019#define PCIE_LCSR_LINK_DIS __BIT(4) /* Link Disable */
1020#define PCIE_LCSR_RETRAIN __BIT(5) /* Retrain Link */
1021#define PCIE_LCSR_COMCLKCFG __BIT(6) /* Common Clock Configuration */
1022#define PCIE_LCSR_EXTNDSYNC __BIT(7) /* Extended Synch */
1023#define PCIE_LCSR_ENCLKPM __BIT(8) /* Enable Clock Power Managmt */
1024#define PCIE_LCSR_HAWD __BIT(9) /* HW Autonomous Width Disable*/
1025#define PCIE_LCSR_LBMIE __BIT(10) /* Link BW Management Intr En */
1026#define PCIE_LCSR_LABIE __BIT(11) /* Link Autonomous BW Intr En */
1027#define PCIE_LCSR_DRSSGNL __BITS(15, 14) /* DRS Signaling */
1028#define PCIE_LCSR_LINKSPEED __BITS(19, 16) /* Link Speed */
1029#define PCIE_LCSR_NLW __BITS(25, 20) /* Negotiated Link Width */
1030#define PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */
1031#define PCIE_LCSR_LINKTRAIN __BIT(11 + 16) /* Link Training */
1032#define PCIE_LCSR_SLOTCLKCFG __BIT(12 + 16) /* Slot Clock Configuration */
1033#define PCIE_LCSR_DLACTIVE __BIT(13 + 16) /* Data Link Layer Link Active*/
1034#define PCIE_LCSR_LINK_BW_MGMT __BIT(14 + 16) /* Link BW Management Status */
1035#define PCIE_LCSR_LINK_AUTO_BW __BIT(15 + 16) /* Link Autonomous BW Status */
1036#define PCIE_SLCAP 0x14 /* Slot Capabilities Register */
1037#define PCIE_SLCAP_ABP __BIT(0) /* Attention Button Present */
1038#define PCIE_SLCAP_PCP __BIT(1) /* Power Controller Present */
1039#define PCIE_SLCAP_MSP __BIT(2) /* MRL Sensor Present */
1040#define PCIE_SLCAP_AIP __BIT(3) /* Attention Indicator Present*/
1041#define PCIE_SLCAP_PIP __BIT(4) /* Power Indicator Present */
1042#define PCIE_SLCAP_HPS __BIT(5) /* Hot-Plug Surprise */
1043#define PCIE_SLCAP_HPC __BIT(6) /* Hot-Plug Capable */
1044#define PCIE_SLCAP_SPLV __BITS(14, 7) /* Slot Power Limit Value */
1045#define PCIE_SLCAP_SPLS __BITS(16, 15) /* Slot Power Limit Scale */
1046#define PCIE_SLCAP_EIP __BIT(17) /* Electromechanical Interlock*/
1047#define PCIE_SLCAP_NCCS __BIT(18) /* No Command Completed Supp. */
1048#define PCIE_SLCAP_PSN __BITS(31, 19) /* Physical Slot Number */
1049#define PCIE_SLCSR 0x18 /* Slot Control & Status Register */
1050#define PCIE_SLCSR_ABE __BIT(0) /* Attention Button Pressed En*/
1051#define PCIE_SLCSR_PFE __BIT(1) /* Power Button Pressed Enable*/
1052#define PCIE_SLCSR_MSE __BIT(2) /* MRL Sensor Changed Enable */
1053#define PCIE_SLCSR_PDE __BIT(3) /* Presence Detect Changed Ena*/
1054#define PCIE_SLCSR_CCE __BIT(4) /* Command Completed Intr. En */
1055#define PCIE_SLCSR_HPE __BIT(5) /* Hot Plug Interrupt Enable */
1056#define PCIE_SLCSR_AIC __BITS(7, 6) /* Attention Indicator Control*/
1057#define PCIE_SLCSR_PIC __BITS(9, 8) /* Power Indicator Control */
1058#define PCIE_SLCSR_IND_ON 0x1 /* Attn/Power Indicator On */
1059#define PCIE_SLCSR_IND_BLINK 0x2 /* Attn/Power Indicator Blink */
1060#define PCIE_SLCSR_IND_OFF 0x3 /* Attn/Power Indicator Off */
1061#define PCIE_SLCSR_PCC __BIT(10) /*
1062 * Power Controller Control:
1063 * 0: Power on, 1: Power off.
1064 */
1065#define PCIE_SLCSR_EIC __BIT(11) /* Electromechanical Interlock*/
1066#define PCIE_SLCSR_DLLSCE __BIT(12) /* DataLinkLayer State Changed*/
1067#define PCIE_SLCSR_AUTOSPLDIS __BIT(13) /* Auto Slot Power Limit Dis. */
1068#define PCIE_SLCSR_ABP __BIT(0 + 16) /* Attention Button Pressed */
1069#define PCIE_SLCSR_PFD __BIT(1 + 16) /* Power Fault Detected */
1070#define PCIE_SLCSR_MSC __BIT(2 + 16) /* MRL Sensor Changed */
1071#define PCIE_SLCSR_PDC __BIT(3 + 16) /* Presence Detect Changed */
1072#define PCIE_SLCSR_CC __BIT(4 + 16) /* Command Completed */
1073#define PCIE_SLCSR_MS __BIT(5 + 16) /* MRL Sensor State */
1074#define PCIE_SLCSR_PDS __BIT(6 + 16) /* Presence Detect State */
1075#define PCIE_SLCSR_EIS __BIT(7 + 16) /* Electromechanical Interlock*/
1076#define PCIE_SLCSR_LACS __BIT(8 + 16) /* Data Link Layer State Chg. */
1077#define PCIE_RCR 0x1c /* Root Control & Capabilities Reg. */
1078#define PCIE_RCR_SERR_CER __BIT(0) /* SERR on Correctable Err. En*/
1079#define PCIE_RCR_SERR_NFER __BIT(1) /* SERR on Non-Fatal Error En */
1080#define PCIE_RCR_SERR_FER __BIT(2) /* SERR on Fatal Error Enable */
1081#define PCIE_RCR_PME_IE __BIT(3) /* PME Interrupt Enable */
1082#define PCIE_RCR_CRS_SVE __BIT(4) /* CRS Software Visibility En */
1083#define PCIE_RCR_CRS_SV __BIT(16) /* CRS Software Visibility */
1084#define PCIE_RSR 0x20 /* Root Status Register */
1085#define PCIE_RSR_PME_REQESTER __BITS(15, 0) /* PME Requester ID */
1086#define PCIE_RSR_PME_STAT __BIT(16) /* PME Status */
1087#define PCIE_RSR_PME_PEND __BIT(17) /* PME Pending */
1088#define PCIE_DCAP2 0x24 /* Device Capabilities 2 Register */
1089#define PCIE_DCAP2_COMPT_RANGE __BITS(3,0) /* Compl. Timeout Ranges Supp */
1090#define PCIE_DCAP2_COMPT_DIS __BIT(4) /* Compl. Timeout Disable Supp*/
1091#define PCIE_DCAP2_ARI_FWD __BIT(5) /* ARI Forward Supported */
1092#define PCIE_DCAP2_ATOM_ROUT __BIT(6) /* AtomicOp Routing Supported */
1093#define PCIE_DCAP2_32ATOM __BIT(7) /* 32bit AtomicOp Compl. Supp */
1094#define PCIE_DCAP2_64ATOM __BIT(8) /* 64bit AtomicOp Compl. Supp */
1095#define PCIE_DCAP2_128CAS __BIT(9) /* 128bit Cas Completer Supp. */
1096#define PCIE_DCAP2_NO_ROPR_PASS __BIT(10) /* No RO-enabled PR-PR Passng */
1097#define PCIE_DCAP2_LTR_MEC __BIT(11) /* LTR Mechanism Supported */
1098#define PCIE_DCAP2_TPH_COMP __BITS(13, 12) /* TPH Completer Supported */
1099#define PCIE_DCAP2_LNSYSCLS __BITS(15, 14) /* LN System CLS */
1100#define PCIE_DCAP2_OBFF __BITS(19, 18) /* Optimized Buffer Flush/Fill*/
1101#define PCIE_DCAP2_EXTFMT_FLD __BIT(20) /* Extended Fmt Field Support */
1102#define PCIE_DCAP2_EETLP_PREF __BIT(21) /* End-End TLP Prefix Support */
1103#define PCIE_DCAP2_MAX_EETLP __BITS(23, 22) /* Max End-End TLP Prefix Sup */
1104#define PCIE_DCAP2_EMGPWRRED __BITS(25, 24) /* Emergency Power Reduc. Sup */
1105#define PCIE_DCAP2_EMGPWRRED_INI __BIT(26) /* Emrg. Pwr. Reduc. Ini. Req */
1106#define PCIE_DCAP2_FRS __BIT(31) /* FRS Supported */
1107#define PCIE_DCSR2 0x28 /* Device Control & Status 2 Register */
1108#define PCIE_DCSR2_COMPT_VAL __BITS(3, 0) /* Completion Timeout Value */
1109#define PCIE_DCSR2_COMPT_DIS __BIT(4) /* Completion Timeout Disable */
1110#define PCIE_DCSR2_ARI_FWD __BIT(5) /* ARI Forwarding Enable */
1111#define PCIE_DCSR2_ATOM_REQ __BIT(6) /* AtomicOp Requester Enable */
1112#define PCIE_DCSR2_ATOM_EBLK __BIT(7) /* AtomicOp Egress Blocking */
1113#define PCIE_DCSR2_IDO_REQ __BIT(8) /* IDO Request Enable */
1114#define PCIE_DCSR2_IDO_COMP __BIT(9) /* IDO Completion Enable */
1115#define PCIE_DCSR2_LTR_MEC __BIT(10) /* LTR Mechanism Enable */
1116#define PCIE_DCSR2_EMGPWRRED_REQ __BIT(11) /* Emergency Power Reduc. Req */
1117#define PCIE_DCSR2_OBFF_EN __BITS(14, 13) /* OBFF Enable */
1118#define PCIE_DCSR2_EETLP __BIT(15) /* End-End TLP Prefix Blcking */
1119#define PCIE_LCAP2 0x2c /* Link Capabilities 2 Register */
1120#define PCIE_LCAP2_SUP_LNKSV __BITS(7, 1) /* Supported Link Speeds Vect */
1121#define PCIE_LCAP2_CROSSLNK __BIT(8) /* Crosslink Supported */
1122#define PCIE_LCAP2_LOWSKPOS_GENSUPPSV __BITS(15, 9)
1123 /* Lower SKP OS Generation Supp. Spd. Vect */
1124#define PCIE_LCAP2_LOWSKPOS_RECSUPPSV __BITS(22, 16)
1125 /* Lower SKP OS Reception Supp. Spd. Vect */
1126#define PCIE_LCAP2_RETIMERPD __BIT(23) /* Retimer Presence Detect */
1127#define PCIE_LCAP2_DRS __BIT(31) /* DRS Supported */
1128#define PCIE_LCSR2 0x30 /* Link Control & Status 2 Register */
1129#define PCIE_LCSR2_TGT_LSPEED __BITS(3, 0) /* Target Link Speed */
1130#define PCIE_LCSR2_ENT_COMPL __BIT(4) /* Enter Compliance */
1131#define PCIE_LCSR2_HW_AS_DIS __BIT(5) /* HW Autonomous Speed Disabl */
1132#define PCIE_LCSR2_SEL_DEEMP __BIT(6) /* Selectable De-emphasis */
1133#define PCIE_LCSR2_TX_MARGIN __BITS(9, 7) /* Transmit Margin */
1134#define PCIE_LCSR2_EN_MCOMP __BIT(10) /* Enter Modified Compliance */
1135#define PCIE_LCSR2_COMP_SOS __BIT(11) /* Compliance SOS */
1136#define PCIE_LCSR2_COMP_DEEMP __BITS(15, 12) /* Compliance Present/De-emph */
1137#define PCIE_LCSR2_DEEMP_LVL __BIT(0 + 16) /* Current De-emphasis Level */
1138#define PCIE_LCSR2_EQ_COMPL __BIT(1 + 16) /* Equalization Complete */
1139#define PCIE_LCSR2_EQP1_SUC __BIT(2 + 16) /* Equaliz Phase 1 Successful */
1140#define PCIE_LCSR2_EQP2_SUC __BIT(3 + 16) /* Equaliz Phase 2 Successful */
1141#define PCIE_LCSR2_EQP3_SUC __BIT(4 + 16) /* Equaliz Phase 3 Successful */
1142#define PCIE_LCSR2_LNKEQ_REQ __BIT(5 + 16) /* Link Equalization Request */
1143#define PCIE_LCSR2_RETIMERPD __BIT(6 + 16) /* Retimer Presence Detected */
1144#define PCIE_LCSR2_DSCOMPN __BITS(30, 28) /* Downstream Component Pres. */
1145#define PCIE_DSCOMPN_DOWN_NOTDETERM 0x00 /* LD: Presence Not Determin.*/
1146#define PCIE_DSCOMPN_DOWN_NOTPRES 0x01 /* LD: Component Not Present */
1147#define PCIE_DSCOMPN_DOWN_PRES 0x02 /* LD: Component Present */
1148 /* 0x03 is reserved */
1149#define PCIE_DSCOMPN_UP_PRES 0x04 /* LU: Component Present */
1150#define PCIE_DSCOMPN_UP_PRES_DRS 0x05 /* LU: Comp Pres and DRS RCV */
1151#define PCIE_LCSR2_DRSRCV __BIT(15 + 16) /* DRS Message Received */
1152
1153#define PCIE_SLCAP2 0x34 /* Slot Capabilities 2 Register */
1154#define PCIE_SLCSR2 0x38 /* Slot Control & Status 2 Register */
1155
1156/*
1157 * Other than Root Complex Integrated Endpoint and Root Complex Event Collector
1158 * have link related registers.
1159 */
1160#define PCIE_HAS_LINKREGS(type) (((type) != PCIE_XCAP_TYPE_ROOT_INTEP) && \
1161 ((type) != PCIE_XCAP_TYPE_ROOT_EVNTC))
1162
1163/* Only root port and root complex event collector have PCIE_RCR & PCIE_RSR */
1164#define PCIE_HAS_ROOTREGS(type) (((type) == PCIE_XCAP_TYPE_ROOT) || \
1165 ((type) == PCIE_XCAP_TYPE_ROOT_EVNTC))
1166
1167
1168/*
1169 * Capability ID: 0x11
1170 * MSIX
1171 */
1172
1173#define PCI_MSIX_CTL 0x00
1174#define PCI_MSIX_CTL_ENABLE 0x80000000
1175#define PCI_MSIX_CTL_FUNCMASK 0x40000000
1176#define PCI_MSIX_CTL_TBLSIZE_MASK 0x07ff0000
1177#define PCI_MSIX_CTL_TBLSIZE_SHIFT 16
1178#define PCI_MSIX_CTL_TBLSIZE(ofs) ((((ofs) & PCI_MSIX_CTL_TBLSIZE_MASK) \
1179 >> PCI_MSIX_CTL_TBLSIZE_SHIFT) + 1)
1180/*
1181 * 2nd DWORD is the Table Offset
1182 */
1183#define PCI_MSIX_TBLOFFSET 0x04
1184#define PCI_MSIX_TBLOFFSET_MASK __BITS(31, 3)
1185#define PCI_MSIX_TBLBIR_MASK __BITS(2, 0)
1186/*
1187 * 3rd DWORD is the Pending Bitmap Array Offset
1188 */
1189#define PCI_MSIX_PBAOFFSET 0x08
1190#define PCI_MSIX_PBAOFFSET_MASK __BITS(31, 3)
1191#define PCI_MSIX_PBABIR_MASK __BITS(2, 0)
1192
1193#define PCI_MSIX_TABLE_ENTRY_SIZE 16
1194#define PCI_MSIX_TABLE_ENTRY_ADDR_LO 0x0
1195#define PCI_MSIX_TABLE_ENTRY_ADDR_HI 0x4
1196#define PCI_MSIX_TABLE_ENTRY_DATA 0x8
1197#define PCI_MSIX_TABLE_ENTRY_VECTCTL 0xc
1198struct pci_msix_table_entry {
1199 uint32_t pci_msix_addr_lo;
1200 uint32_t pci_msix_addr_hi;
1201 uint32_t pci_msix_value;
1202 uint32_t pci_msix_vector_control;
1203};
1204#define PCI_MSIX_VECTCTL_MASK __BIT(0)
1205#define PCI_MSIX_VECTCTL_STLO __BITS(23, 16) /* ST lower */
1206#define PCI_MSIX_VECTCTL_STUP __BITS(31, 24) /* ST upper */
1207
1208 /* Max number of MSI-X vectors. See PCI-SIG specification. */
1209#define PCI_MSIX_MAX_VECTORS 2048
1210
1211/*
1212 * Capability ID: 0x12
1213 * SATA
1214 */
1215#define PCI_SATA_REV 0x00 /* Revision Register */
1216#define PCI_SATA_REV_MINOR __BITS(19, 16) /* Minor Revision */
1217#define PCI_SATA_REV_MAJOR __BITS(23, 20) /* Major Revision */
1218#define PCI_SATA_BAR 0x04 /* BAR Register */
1219#define PCI_SATA_BAR_SPEC __BITS(3, 0) /* BAR Specifier */
1220#define PCI_SATA_BAR_INCONF __BITS(3, 0) /* All 1 = in config space */
1221#define PCI_SATA_BAR_NUM(x) (__SHIFTOUT((x), PCI_SATA_BAR_SPEC) - 4)
1222#define PCI_SATA_BAR_OFFSET __BITS(23, 4) /* BAR Offset */
1223
1224/*
1225 * Capability ID: 0x13
1226 * Advanced Feature
1227 */
1228#define PCI_AFCAPR 0x00 /* Capabilities */
1229#define PCI_AFCAPR_MASK __BITS(31, 24)
1230#define PCI_AF_LENGTH __BITS(23, 16) /* Structure Length */
1231#define PCI_AF_TP_CAP __BIT(24) /* Transaction Pending */
1232#define PCI_AF_FLR_CAP __BIT(25) /* Function Level Reset */
1233#define PCI_AFCSR 0x04 /* Control & Status register */
1234#define PCI_AFCR_INITIATE_FLR __BIT(0) /* Initiate Function LVL RST */
1235#define PCI_AFSR_TP __BIT(8) /* Transaction Pending */
1236
1237
1238/*
1239 * Interrupt Configuration Register; contains interrupt pin and line.
1240 */
1241#define PCI_INTERRUPT_REG 0x3c
1242
1243typedef u_int8_t pci_intr_latency_t;
1244typedef u_int8_t pci_intr_grant_t;
1245typedef u_int8_t pci_intr_pin_t;
1246typedef u_int8_t pci_intr_line_t;
1247
1248#define PCI_MAX_LAT_SHIFT 24
1249#define PCI_MAX_LAT_MASK 0xff
1250#define PCI_MAX_LAT(icr) \
1251 (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
1252
1253#define PCI_MIN_GNT_SHIFT 16
1254#define PCI_MIN_GNT_MASK 0xff
1255#define PCI_MIN_GNT(icr) \
1256 (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
1257
1258#define PCI_INTERRUPT_GRANT_SHIFT 24
1259#define PCI_INTERRUPT_GRANT_MASK 0xff
1260#define PCI_INTERRUPT_GRANT(icr) \
1261 (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)
1262
1263#define PCI_INTERRUPT_LATENCY_SHIFT 16
1264#define PCI_INTERRUPT_LATENCY_MASK 0xff
1265#define PCI_INTERRUPT_LATENCY(icr) \
1266 (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)
1267
1268#define PCI_INTERRUPT_PIN_SHIFT 8
1269#define PCI_INTERRUPT_PIN_MASK 0xff
1270#define PCI_INTERRUPT_PIN(icr) \
1271 (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
1272
1273#define PCI_INTERRUPT_LINE_SHIFT 0
1274#define PCI_INTERRUPT_LINE_MASK 0xff
1275#define PCI_INTERRUPT_LINE(icr) \
1276 (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
1277
1278#define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \
1279 ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \
1280 (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \
1281 (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \
1282 (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT))
1283
1284#define PCI_INTERRUPT_PIN_NONE 0x00
1285#define PCI_INTERRUPT_PIN_A 0x01
1286#define PCI_INTERRUPT_PIN_B 0x02
1287#define PCI_INTERRUPT_PIN_C 0x03
1288#define PCI_INTERRUPT_PIN_D 0x04
1289#define PCI_INTERRUPT_PIN_MAX 0x04
1290
1291/* Header Type 1 (Bridge) configuration registers */
1292#define PCI_BRIDGE_BUS_REG 0x18
1293#define PCI_BRIDGE_BUS_PRIMARY __BITS(0, 7)
1294#define PCI_BRIDGE_BUS_SECONDARY __BITS(8, 15)
1295#define PCI_BRIDGE_BUS_SUBORDINATE __BITS(16, 23)
1296#define PCI_BRIDGE_BUS_SEC_LATTIMER __BITS(24, 31)
1297#define PCI_BRIDGE_BUS_NUM_PRIMARY(reg) \
1298 ((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_PRIMARY))
1299#define PCI_BRIDGE_BUS_NUM_SECONDARY(reg) \
1300 ((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SECONDARY))
1301#define PCI_BRIDGE_BUS_NUM_SUBORDINATE(reg) \
1302 ((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SUBORDINATE))
1303#define PCI_BRIDGE_BUS_SEC_LATTIMER_VAL(reg) \
1304 ((uint32_t)__SHIFTOUT((reg), PCI_BRIDGE_BUS_SEC_LATTIMER))
1305
1306/* Minimum size of the window */
1307#define PCI_BRIDGE_IO_MIN 0x00001000UL
1308#define PCI_BRIDGE_MEM_MIN 0x00100000UL
1309
1310#define PCI_BRIDGE_STATIO_REG 0x1c
1311#define PCI_BRIDGE_STATIO_IOBASE __BITS(0, 7)
1312#define PCI_BRIDGE_STATIO_IOLIMIT __BITS(8, 15)
1313#define PCI_BRIDGE_STATIO_STATUS __BITS(16, 31)
1314#define PCI_BRIDGE_STATIO_IOADDR 0xf0
1315#define PCI_BRIDGE_STATIO_IOADDR_TYPE 0x0f /* Read only */
1316#define PCI_BRIDGE_STATIO_IOADDR_32 0x01
1317#define PCI_BRIDGE_STATIO_IOBASE_ADDR(reg) \
1318 ((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOBASE) \
1319 & PCI_BRIDGE_STATIO_IOADDR) << 8)
1320#define PCI_BRIDGE_STATIO_IOLIMIT_ADDR(reg) \
1321 (((__SHIFTOUT((reg), PCI_BRIDGE_STATIO_IOLIMIT) \
1322 & PCI_BRIDGE_STATIO_IOADDR) << 8) | (PCI_BRIDGE_IO_MIN - 1))
1323#define PCI_BRIDGE_IO_32BITS(reg) \
1324 (((reg) & PCI_BRIDGE_STATIO_IOADDR_TYPE) == PCI_BRIDGE_STATIO_IOADDR_32)
1325
1326#define PCI_BRIDGE_MEMORY_REG 0x20
1327#define PCI_BRIDGE_MEMORY_BASE __BITS(0, 15)
1328#define PCI_BRIDGE_MEMORY_LIMIT __BITS(16, 31)
1329#define PCI_BRIDGE_MEMORY_ADDR 0xfff0
1330#define PCI_BRIDGE_MEMORY_BASE_ADDR(reg) \
1331 ((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_BASE) \
1332 & PCI_BRIDGE_MEMORY_ADDR) << 16)
1333#define PCI_BRIDGE_MEMORY_LIMIT_ADDR(reg) \
1334 (((__SHIFTOUT((reg), PCI_BRIDGE_MEMORY_LIMIT) \
1335 & PCI_BRIDGE_MEMORY_ADDR) << 16) | 0x000fffff)
1336
1337#define PCI_BRIDGE_PREFETCHMEM_REG 0x24
1338#define PCI_BRIDGE_PREFETCHMEM_BASE __BITS(0, 15)
1339#define PCI_BRIDGE_PREFETCHMEM_LIMIT __BITS(16, 31)
1340#define PCI_BRIDGE_PREFETCHMEM_ADDR 0xfff0
1341#define PCI_BRIDGE_PREFETCHMEM_BASE_ADDR(reg) \
1342 ((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_BASE) \
1343 & PCI_BRIDGE_PREFETCHMEM_ADDR) << 16)
1344#define PCI_BRIDGE_PREFETCHMEM_LIMIT_ADDR(reg) \
1345 (((__SHIFTOUT((reg), PCI_BRIDGE_PREFETCHMEM_LIMIT) \
1346 & PCI_BRIDGE_PREFETCHMEM_ADDR) << 16) | 0x000fffff)
1347#define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf)
1348
1349#define PCI_BRIDGE_PREFETCHBASEUP32_REG 0x28
1350#define PCI_BRIDGE_PREFETCHLIMITUP32_REG 0x2c
1351
1352#define PCI_BRIDGE_IOHIGH_REG 0x30
1353#define PCI_BRIDGE_IOHIGH_BASE __BITS(0, 15)
1354#define PCI_BRIDGE_IOHIGH_LIMIT __BITS(16, 31)
1355
1356#define PCI_BRIDGE_EXPROMADDR_REG 0x38
1357
1358#define PCI_BRIDGE_CONTROL_REG 0x3c /* Upper 16 bit */
1359#define PCI_BRIDGE_CONTROL __BITS(16, 31)
1360#define PCI_BRIDGE_CONTROL_PERE __BIT(16)
1361#define PCI_BRIDGE_CONTROL_SERR __BIT(17)
1362#define PCI_BRIDGE_CONTROL_ISA __BIT(18)
1363#define PCI_BRIDGE_CONTROL_VGA __BIT(19)
1364#define PCI_BRIDGE_CONTROL_VGA16 __BIT(20)
1365#define PCI_BRIDGE_CONTROL_MABRT __BIT(21)
1366#define PCI_BRIDGE_CONTROL_SECBR __BIT(22)
1367#define PCI_BRIDGE_CONTROL_SECFASTB2B __BIT(23)
1368#define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER __BIT(24)
1369#define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER __BIT(25)
1370#define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT __BIT(26)
1371#define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR __BIT(27)
1372/* Reserved (1 << 12) - (1 << 15) */
1373
1374/*
1375 * Vital Product Data resource tags.
1376 */
1377struct pci_vpd_smallres {
1378 uint8_t vpdres_byte0; /* length of data + tag */
1379 /* Actual data. */
1380} __packed;
1381
1382struct pci_vpd_largeres {
1383 uint8_t vpdres_byte0;
1384 uint8_t vpdres_len_lsb; /* length of data only */
1385 uint8_t vpdres_len_msb;
1386 /* Actual data. */
1387} __packed;
1388
1389#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
1390
1391#define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7)
1392#define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf)
1393
1394#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
1395
1396#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */
1397#define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */
1398#define PCI_VPDRES_TYPE_END_TAG 0xf /* small */
1399
1400#define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */
1401#define PCI_VPDRES_TYPE_VPD 0x10 /* large */
1402
1403struct pci_vpd {
1404 uint8_t vpd_key0;
1405 uint8_t vpd_key1;
1406 uint8_t vpd_len; /* length of data only */
1407 /* Actual data. */
1408} __packed;
1409
1410/*
1411 * Recommended VPD fields:
1412 *
1413 * PN Part number of assembly
1414 * FN FRU part number
1415 * EC EC level of assembly
1416 * MN Manufacture ID
1417 * SN Serial Number
1418 *
1419 * Conditionally recommended VPD fields:
1420 *
1421 * LI Load ID
1422 * RL ROM Level
1423 * RM Alterable ROM Level
1424 * NA Network Address
1425 * DD Device Driver Level
1426 * DG Diagnostic Level
1427 * LL Loadable Microcode Level
1428 * VI Vendor ID/Device ID
1429 * FU Function Number
1430 * SI Subsystem Vendor ID/Subsystem ID
1431 *
1432 * Additional VPD fields:
1433 *
1434 * Z0-ZZ User/Product Specific
1435 */
1436
1437/*
1438 * PCI Expansion Rom
1439 */
1440
1441struct pci_rom_header {
1442 uint16_t romh_magic; /* 0xAA55 little endian */
1443 uint8_t romh_reserved[22];
1444 uint16_t romh_data_ptr; /* pointer to pci_rom struct */
1445} __packed;
1446
1447#define PCI_ROM_HEADER_MAGIC 0xAA55 /* little endian */
1448
1449struct pci_rom {
1450 uint32_t rom_signature;
1451 pci_vendor_id_t rom_vendor;
1452 pci_product_id_t rom_product;
1453 uint16_t rom_vpd_ptr; /* reserved in PCI 2.2 */
1454 uint16_t rom_data_len;
1455 uint8_t rom_data_rev;
1456 pci_interface_t rom_interface; /* the class reg is 24-bits */
1457 pci_subclass_t rom_subclass; /* in little endian */
1458 pci_class_t rom_class;
1459 uint16_t rom_len; /* code length / 512 byte */
1460 uint16_t rom_rev; /* code revision level */
1461 uint8_t rom_code_type; /* type of code */
1462 uint8_t rom_indicator;
1463 uint16_t rom_reserved;
1464 /* Actual data. */
1465} __packed;
1466
1467#define PCI_ROM_SIGNATURE 0x52494350 /* "PCIR", endian reversed */
1468#define PCI_ROM_CODE_TYPE_X86 0 /* Intel x86 BIOS */
1469#define PCI_ROM_CODE_TYPE_OFW 1 /* Open Firmware */
1470#define PCI_ROM_CODE_TYPE_HPPA 2 /* HP PA/RISC */
1471#define PCI_ROM_CODE_TYPE_EFI 3 /* EFI Image */
1472
1473#define PCI_ROM_INDICATOR_LAST 0x80
1474
1475/*
1476 * Threshold below which 32bit PCI DMA needs bouncing.
1477 */
1478#define PCI32_DMA_BOUNCE_THRESHOLD 0x100000000ULL
1479
1480/*
1481 * PCI-X 2.0/ PCI-express Extended Capability List
1482 */
1483
1484#define PCI_EXTCAPLIST_BASE 0x100
1485
1486#define PCI_EXTCAPLIST_CAP(ecr) ((ecr) & 0xffff)
1487#define PCI_EXTCAPLIST_VERSION(ecr) (((ecr) >> 16) & 0xf)
1488#define PCI_EXTCAPLIST_NEXT(ecr) (((ecr) >> 20) & 0xfff)
1489
1490/* Extended Capability Identification Numbers */
1491
1492#define PCI_EXTCAP_AER 0x0001 /* Advanced Error Reporting */
1493#define PCI_EXTCAP_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */
1494#define PCI_EXTCAP_SERNUM 0x0003 /* Device Serial Number */
1495#define PCI_EXTCAP_PWRBDGT 0x0004 /* Power Budgeting */
1496#define PCI_EXTCAP_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */
1497#define PCI_EXTCAP_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */
1498#define PCI_EXTCAP_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */
1499#define PCI_EXTCAP_MFVC 0x0008 /* Multi-Function Virtual Channel */
1500#define PCI_EXTCAP_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */
1501#define PCI_EXTCAP_RCRB 0x000a /* RCRB Header */
1502#define PCI_EXTCAP_VENDOR 0x000b /* Vendor Unique */
1503#define PCI_EXTCAP_CAC 0x000c /* Configuration Access Correction -- obsolete */
1504#define PCI_EXTCAP_ACS 0x000d /* Access Control Services */
1505#define PCI_EXTCAP_ARI 0x000e /* Alternative Routing-ID Interpretation */
1506#define PCI_EXTCAP_ATS 0x000f /* Address Translation Services */
1507#define PCI_EXTCAP_SRIOV 0x0010 /* Single Root IO Virtualization */
1508#define PCI_EXTCAP_MRIOV 0x0011 /* Multiple Root IO Virtualization */
1509#define PCI_EXTCAP_MCAST 0x0012 /* Multicast */
1510#define PCI_EXTCAP_PAGE_REQ 0x0013 /* Page Request */
1511#define PCI_EXTCAP_AMD 0x0014 /* Reserved for AMD */
1512#define PCI_EXTCAP_RESIZBAR 0x0015 /* Resizable BAR */
1513#define PCI_EXTCAP_DPA 0x0016 /* Dynamic Power Allocation */
1514#define PCI_EXTCAP_TPH_REQ 0x0017 /* TPH Requester */
1515#define PCI_EXTCAP_LTR 0x0018 /* Latency Tolerance Reporting */
1516#define PCI_EXTCAP_SEC_PCIE 0x0019 /* Secondary PCI Express */
1517#define PCI_EXTCAP_PMUX 0x001a /* Protocol Multiplexing */
1518#define PCI_EXTCAP_PASID 0x001b /* Process Address Space ID */
1519#define PCI_EXTCAP_LNR 0x001c /* LN Requester */
1520#define PCI_EXTCAP_DPC 0x001d /* Downstream Port Containment */
1521#define PCI_EXTCAP_L1PM 0x001e /* L1 PM Substates */
1522#define PCI_EXTCAP_PTM 0x001f /* Precision Time Management */
1523#define PCI_EXTCAP_MPCIE 0x0020 /* M-PCIe */
1524#define PCI_EXTCAP_FRSQ 0x0021 /* Function Reading Status Queueing */
1525#define PCI_EXTCAP_RTR 0x0022 /* Readiness Time Reporting */
1526#define PCI_EXTCAP_DESIGVNDSP 0x0023 /* Designated Vendor-Specific */
1527#define PCI_EXTCAP_VF_RESIZBAR 0x0024 /* VF Resizable BAR */
1528#define PCI_EXTCAP_HIERARCHYID 0x0028 /* Hierarchy ID */
1529#define PCI_EXTCAP_NPEM 0x0029 /* Native PCIe Enclosure Management */
1530
1531/*
1532 * Extended capability ID: 0x0001
1533 * Advanced Error Reporting
1534 */
1535#define PCI_AER_UC_STATUS 0x04 /* Uncorrectable Error Status Reg. */
1536#define PCI_AER_UC_UNDEFINED __BIT(0)
1537#define PCI_AER_UC_DL_PROTOCOL_ERROR __BIT(4)
1538#define PCI_AER_UC_SURPRISE_DOWN_ERROR __BIT(5)
1539#define PCI_AER_UC_POISONED_TLP __BIT(12)
1540#define PCI_AER_UC_FC_PROTOCOL_ERROR __BIT(13)
1541#define PCI_AER_UC_COMPLETION_TIMEOUT __BIT(14)
1542#define PCI_AER_UC_COMPLETER_ABORT __BIT(15)
1543#define PCI_AER_UC_UNEXPECTED_COMPLETION __BIT(16)
1544#define PCI_AER_UC_RECEIVER_OVERFLOW __BIT(17)
1545#define PCI_AER_UC_MALFORMED_TLP __BIT(18)
1546#define PCI_AER_UC_ECRC_ERROR __BIT(19)
1547#define PCI_AER_UC_UNSUPPORTED_REQUEST_ERROR __BIT(20)
1548#define PCI_AER_UC_ACS_VIOLATION __BIT(21)
1549#define PCI_AER_UC_INTERNAL_ERROR __BIT(22)
1550#define PCI_AER_UC_MC_BLOCKED_TLP __BIT(23)
1551#define PCI_AER_UC_ATOMIC_OP_EGRESS_BLOCKED __BIT(24)
1552#define PCI_AER_UC_TLP_PREFIX_BLOCKED_ERROR __BIT(25)
1553#define PCI_AER_UC_POISONTLP_EGRESS_BLOCKED __BIT(26)
1554#define PCI_AER_UC_MASK 0x08 /* Uncorrectable Error Mask Register */
1555 /* Shares bits with UC_STATUS */
1556#define PCI_AER_UC_SEVERITY 0x0c /* Uncorrectable Error Severity Reg. */
1557 /* Shares bits with UC_STATUS */
1558#define PCI_AER_COR_STATUS 0x10 /* Correctable Error Status Register */
1559#define PCI_AER_COR_RECEIVER_ERROR __BIT(0)
1560#define PCI_AER_COR_BAD_TLP __BIT(6)
1561#define PCI_AER_COR_BAD_DLLP __BIT(7)
1562#define PCI_AER_COR_REPLAY_NUM_ROLLOVER __BIT(8)
1563#define PCI_AER_COR_REPLAY_TIMER_TIMEOUT __BIT(12)
1564#define PCI_AER_COR_ADVISORY_NF_ERROR __BIT(13)
1565#define PCI_AER_COR_INTERNAL_ERROR __BIT(14)
1566#define PCI_AER_COR_HEADER_LOG_OVERFLOW __BIT(15)
1567#define PCI_AER_COR_MASK 0x14 /* Correctable Error Mask Register */
1568 /* Shares bits with COR_STATUS */
1569#define PCI_AER_CAP_CONTROL 0x18 /* AE Capabilities and Control Reg. */
1570#define PCI_AER_FIRST_ERROR_PTR __BITS(4, 0)
1571#define PCI_AER_FIRST_ERROR_PTR_S 0
1572#define PCI_AER_FIRST_ERROR_PTR_M 0x1f
1573#define PCI_AER_ECRC_GEN_CAPABLE __BIT(5)
1574#define PCI_AER_ECRC_GEN_ENABLE __BIT(6)
1575#define PCI_AER_ECRC_CHECK_CAPABLE __BIT(7)
1576#define PCI_AER_ECRC_CHECK_ENABLE __BIT(8)
1577#define PCI_AER_MULT_HDR_CAPABLE __BIT(9)
1578#define PCI_AER_MULT_HDR_ENABLE __BIT(10)
1579#define PCI_AER_TLP_PREFIX_LOG_PRESENT __BIT(11)
1580#define PCI_AER_COMPTOUTPRFXHDRLOG_CAP __BIT(12)
1581#define PCI_AER_HEADER_LOG 0x1c /* Header Log Register */
1582#define PCI_AER_ROOTERR_CMD 0x2c /* Root Error Command Register */
1583 /* Only for root complex ports */
1584#define PCI_AER_ROOTERR_COR_ENABLE __BIT(0)
1585#define PCI_AER_ROOTERR_NF_ENABLE __BIT(1)
1586#define PCI_AER_ROOTERR_F_ENABLE __BIT(2)
1587#define PCI_AER_ROOTERR_STATUS 0x30 /* Root Error Status Register */
1588 /* Only for root complex ports */
1589#define PCI_AER_ROOTERR_COR_ERR __BIT(0)
1590#define PCI_AER_ROOTERR_MULTI_COR_ERR __BIT(1)
1591#define PCI_AER_ROOTERR_UC_ERR __BIT(2)
1592#define PCI_AER_ROOTERR_MULTI_UC_ERR __BIT(3)
1593#define PCI_AER_ROOTERR_FIRST_UC_FATAL __BIT(4)
1594#define PCI_AER_ROOTERR_NF_ERR __BIT(5)
1595#define PCI_AER_ROOTERR_F_ERR __BIT(6)
1596#define PCI_AER_ROOTERR_INT_MESSAGE __BITS(31, 27)
1597#define PCI_AER_ROOTERR_INT_MESSAGE_S 27
1598#define PCI_AER_ROOTERR_INT_MESSAGE_M 0x1f
1599#define PCI_AER_ERRSRC_ID 0x34 /* Error Source Identification Reg. */
1600#define PCI_AER_ERRSRC_ID_ERR_COR __BITS(15, 0)
1601#define PCI_AER_ERRSRC_ID_ERR_COR_S 0
1602#define PCI_AER_ERRSRC_ID_ERR_COR_M 0xffff
1603#define PCI_AER_ERRSRC_ID_ERR_UC __BITS(31, 16)
1604#define PCI_AER_ERRSRC_ID_ERR_UC_S 16
1605#define PCI_AER_ERRSRC_ID_ERR_UC_M 0xffff
1606 /* Only for root complex ports */
1607#define PCI_AER_TLP_PREFIX_LOG 0x38 /*TLP Prefix Log Register */
1608 /* Only for TLP prefix functions */
1609
1610/*
1611 * Extended capability ID: 0x0002, 0x0009
1612 * Virtual Channel
1613 */
1614#define PCI_VC_CAP1 0x04 /* Port VC Capability Register 1 */
1615#define PCI_VC_CAP1_EXT_COUNT __BITS(2, 0)
1616#define PCI_VC_CAP1_EXT_COUNT_S 0
1617#define PCI_VC_CAP1_EXT_COUNT_M 0x7
1618#define PCI_VC_CAP1_LOWPRI_EXT_COUNT __BITS(6, 4)
1619#define PCI_VC_CAP1_LOWPRI_EXT_COUNT_S 4
1620#define PCI_VC_CAP1_LOWPRI_EXT_COUNT_M 0x7
1621#define PCI_VC_CAP1_REFCLK __BITS(9, 8)
1622#define PCI_VC_CAP1_REFCLK_S 8
1623#define PCI_VC_CAP1_REFCLK_M 0x3
1624#define PCI_VC_CAP1_REFCLK_100NS 0x0
1625#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE __BITS(11, 10)
1626#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_S 10
1627#define PCI_VC_CAP1_PORT_ARB_TABLE_SIZE_M 0x3
1628#define PCI_VC_CAP2 0x08 /* Port VC Capability Register 2 */
1629#define PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME __BIT(0)
1630#define PCI_VC_CAP2_ARB_CAP_WRR_32 __BIT(1)
1631#define PCI_VC_CAP2_ARB_CAP_WRR_64 __BIT(2)
1632#define PCI_VC_CAP2_ARB_CAP_WRR_128 __BIT(3)
1633#define PCI_VC_CAP2_ARB_TABLE_OFFSET __BITS(31, 24)
1634#define PCI_VC_CAP2_ARB_TABLE_OFFSET_S 24
1635#define PCI_VC_CAP2_ARB_TABLE_OFFSET_M 0xff
1636#define PCI_VC_CONTROL 0x0c /* Port VC Control Register (16bit) */
1637#define PCI_VC_CONTROL_LOAD_VC_ARB_TABLE __BIT(0)
1638#define PCI_VC_CONTROL_VC_ARB_SELECT __BITS(3, 1)
1639#define PCI_VC_CONTROL_VC_ARB_SELECT_S 1
1640#define PCI_VC_CONTROL_VC_ARB_SELECT_M 0x7
1641#define PCI_VC_STATUS 0x0e /* Port VC Status Register (16bit) */
1642#define PCI_VC_STATUS_LOAD_VC_ARB_TABLE __BIT(0)
1643#define PCI_VC_RESOURCE_CAP(n) (0x10 + ((n) * 0x0c)) /* VC Resource Capability Register */
1644#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME __BIT(0)
1645#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32 __BIT(1)
1646#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64 __BIT(2)
1647#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128 __BIT(3)
1648#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128 __BIT(4)
1649#define PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256 __BIT(5)
1650#define PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH __BIT(14)
1651#define PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS __BIT(15)
1652#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS __BITS(22, 16)
1653#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_S 16
1654#define PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS_M 0x7f
1655#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET __BITS(31, 24)
1656#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S 24
1657#define PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_M 0xff
1658#define PCI_VC_RESOURCE_CTL(n) (0x14 + ((n) * 0x0c)) /* VC Resource Control Register */
1659#define PCI_VC_RESOURCE_CTL_TCVC_MAP __BITS(7, 0)
1660#define PCI_VC_RESOURCE_CTL_TCVC_MAP_S 0
1661#define PCI_VC_RESOURCE_CTL_TCVC_MAP_M 0xff
1662#define PCI_VC_RESOURCE_CTL_LOAD_PORT_ARB_TABLE __BIT(16)
1663#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT __BITS(19, 17)
1664#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_S 17
1665#define PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT_M 0x7
1666#define PCI_VC_RESOURCE_CTL_VC_ID __BITS(26, 24)
1667#define PCI_VC_RESOURCE_CTL_VC_ID_S 24
1668#define PCI_VC_RESOURCE_CTL_VC_ID_M 0x7
1669#define PCI_VC_RESOURCE_CTL_VC_ENABLE __BIT(31)
1670#define PCI_VC_RESOURCE_STA(n) (0x18 + ((n) * 0x0c)) /* VC Resource Status Register */
1671#define PCI_VC_RESOURCE_STA_PORT_ARB_TABLE __BIT(0)
1672#define PCI_VC_RESOURCE_STA_VC_NEG_PENDING __BIT(1)
1673
1674/*
1675 * Extended capability ID: 0x0003
1676 * Serial Number
1677 */
1678#define PCI_SERIAL_LOW 0x04
1679#define PCI_SERIAL_HIGH 0x08
1680
1681/*
1682 * Extended capability ID: 0x0004
1683 * Power Budgeting
1684 */
1685#define PCI_PWRBDGT_DSEL 0x04 /* Data Select */
1686#define PCI_PWRBDGT_DATA 0x08 /* Data */
1687#define PCI_PWRBDGT_DATA_BASEPWR __BITS(7, 0) /* Base Power */
1688#define PCI_PWRBDGT_DATA_SCALE __BITS(9, 8) /* Data Scale */
1689#define PCI_PWRBDGT_PM_SUBSTAT __BITS(12, 10) /* PM Sub State */
1690#define PCI_PWRBDGT_PM_STAT __BITS(14, 13) /* PM State */
1691#define PCI_PWRBDGT_TYPE __BITS(17, 15) /* Type */
1692#define PCI_PWRBDGT_PWRRAIL __BITS(20, 18) /* Power Rail */
1693#define PCI_PWRBDGT_CAP 0x0c /* Capability */
1694#define PCI_PWRBDGT_CAP_SYSALLOC __BIT(0) /* System Allocated */
1695
1696/*
1697 * Extended capability ID: 0x0005
1698 * Root Complex Link Declaration
1699 */
1700#define PCI_RCLINK_DCL_ESDESC 0x04 /* Element Self Description */
1701#define PCI_RCLINK_DCL_ESDESC_ELMTYPE __BITS(3, 0) /* Element Type */
1702#define PCI_RCLINK_DCL_ESDESC_NUMLINKENT __BITS(15, 8) /* Num of Link Entries*/
1703#define PCI_RCLINK_DCL_ESDESC_COMPID __BITS(23, 16) /* Component ID */
1704#define PCI_RCLINK_DCL_ESDESC_PORTNUM __BITS(31, 24) /* Port Number */
1705#define PCI_RCLINK_DCL_LINKENTS 0x10 /* Link Entries */
1706#define PCI_RCLINK_DCL_LINKDESC(x) /* Link Description */ \
1707 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16))
1708#define PCI_RCLINK_DCL_LINKDESC_LVALID __BIT(0) /* Link Valid */
1709#define PCI_RCLINK_DCL_LINKDESC_LTYPE __BIT(1) /* Link Type */
1710#define PCI_RCLINK_DCL_LINKDESC_ARCRBH __BIT(2) /* Associate RCRB Header */
1711#define PCI_RCLINK_DCL_LINKDESC_TCOMPID __BITS(23, 16) /* Target Component ID*/
1712#define PCI_RCLINK_DCL_LINKDESC_TPNUM __BITS(31, 24) /* Target Port Number */
1713#define PCI_RCLINK_DCL_LINKADDR_LT0_LO(x) /* LT0: Link Address Low */ \
1714 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x08)
1715#define PCI_RCLINK_DCL_LINKADDR_LT0_HI(x) /* LT0: Link Address High */ \
1716 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x0c)
1717#define PCI_RCLINK_DCL_LINKADDR_LT1_LO(x) /* LT1: Config Space (low) */ \
1718 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x08)
1719#define PCI_RCLINK_DCL_LINKADDR_LT1_N __BITS(2, 0) /* N */
1720#define PCI_RCLINK_DCL_LINKADDR_LT1_FUNC __BITS(14, 12) /* Function Number */
1721#define PCI_RCLINK_DCL_LINKADDR_LT1_DEV __BITS(19, 15) /* Device Number */
1722#define PCI_RCLINK_DCL_LINKADDR_LT1_BUS(N) __BITS(19 + (N), 20) /* Bus Number*/
1723#define PCI_RCLINK_DCL_LINKADDR_LT1_BAL(N) __BITS(31, 20 + (N)) /* BAddr(L) */
1724#define PCI_RCLINK_DCL_LINKADDR_LT1_HI(x) /* LT1: Config Space Base Addr(H) */\
1725 (PCI_RCLINK_DCL_LINKENTS + ((x) * 16) + 0x0c)
1726
1727/*
1728 * Extended capability ID: 0x0006
1729 * Root Complex Internal Link Control
1730 */
1731
1732/*
1733 * Extended capability ID: 0x0007
1734 * Root Complex Event Collector Association
1735 */
1736#define PCI_RCEC_ASSOC_ASSOCBITMAP 0x04 /* Association Bitmap */
1737#define PCI_RCEC_ASSOC_ASSOCBUSNUM 0x08 /* Associcated Bus Number */
1738#define PCI_RCEC_ASSOCBUSNUM_RCECNEXT __BITS(15, 8) /* RCEC Next Bus */
1739#define PCI_RCEC_ASSOCBUSNUM_RCECLAST __BITS(23, 16) /* RCEC Last Bus */
1740
1741/*
1742 * Extended capability ID: 0x0008
1743 * Multi-Function Virtual Channel
1744 */
1745
1746/*
1747 * Extended capability ID: 0x0009
1748 * Virtual Channel if MFVC Ext Cap set
1749 */
1750
1751/*
1752 * Extended capability ID: 0x000a
1753 * RCRB Header
1754 */
1755
1756/*
1757 * Extended capability ID: 0x000b
1758 * Vendor Unique
1759 */
1760
1761/*
1762 * Extended capability ID: 0x000c
1763 * Configuration Access Correction
1764 */
1765
1766/*
1767 * Extended capability ID: 0x000d
1768 * Access Control Services
1769 */
1770#define PCI_ACS_CAP 0x04 /* Capability Register */
1771#define PCI_ACS_CAP_V __BIT(0) /* Source Validation */
1772#define PCI_ACS_CAP_B __BIT(1) /* Transaction Blocking */
1773#define PCI_ACS_CAP_R __BIT(2) /* P2P Request Redirect */
1774#define PCI_ACS_CAP_C __BIT(3) /* P2P Completion Redirect */
1775#define PCI_ACS_CAP_U __BIT(4) /* Upstream Forwarding */
1776#define PCI_ACS_CAP_E __BIT(5) /* Egress Control */
1777#define PCI_ACS_CAP_T __BIT(6) /* Direct Translated P2P */
1778#define PCI_ACS_CAP_ECVSIZE __BITS(15, 8) /* Egress Control Vector Size */
1779#define PCI_ACS_CTL 0x04 /* Control Register */
1780#define PCI_ACS_CTL_V __BIT(0 + 16) /* Source Validation Enable */
1781#define PCI_ACS_CTL_B __BIT(1 + 16) /* Transaction Blocking Enable */
1782#define PCI_ACS_CTL_R __BIT(2 + 16) /* P2P Request Redirect Enable */
1783#define PCI_ACS_CTL_C __BIT(3 + 16) /* P2P Completion Redirect Enable */
1784#define PCI_ACS_CTL_U __BIT(4 + 16) /* Upstream Forwarding Enable */
1785#define PCI_ACS_CTL_E __BIT(5 + 16) /* Egress Control Enable */
1786#define PCI_ACS_CTL_T __BIT(6 + 16) /* Direct Translated P2P Enable */
1787#define PCI_ACS_ECV 0x08 /* Egress Control Vector */
1788
1789/*
1790 * Extended capability ID: 0x000e
1791 * ARI
1792 */
1793#define PCI_ARI_CAP 0x04 /* Capability Register */
1794#define PCI_ARI_CAP_M __BIT(0) /* MFVC Function Groups Cap. */
1795#define PCI_ARI_CAP_A __BIT(1) /* ACS Function Groups Cap. */
1796#define PCI_ARI_CAP_NXTFN __BITS(15, 8) /* Next Function Number */
1797#define PCI_ARI_CTL 0x04 /* Control Register */
1798#define PCI_ARI_CTL_M __BIT(16) /* MFVC Function Groups Ena. */
1799#define PCI_ARI_CTL_A __BIT(17) /* ACS Function Groups Ena. */
1800#define PCI_ARI_CTL_FUNCGRP __BITS(22, 20) /* Function Group */
1801
1802/*
1803 * Extended capability ID: 0x000f
1804 * Address Translation Services
1805 */
1806#define PCI_ATS_CAP 0x04 /* Capability Register */
1807#define PCI_ATS_CAP_INVQDEPTH __BITS(4, 0) /* Invalidate Queue Depth */
1808#define PCI_ATS_CAP_PALIGNREQ __BIT(5) /* Page Aligned Request */
1809#define PCI_ATS_CAP_GLOBALINVL __BIT(6) /* Global Invalidate Support */
1810#define PCI_ATS_CAP_RELAXORD __BIT(7) /* Relaxed Ordering */
1811#define PCI_ATS_CTL 0x04 /* Control Register */
1812#define PCI_ATS_CTL_STU __BITS(20, 16) /* Smallest Translation Unit */
1813#define PCI_ATS_CTL_EN __BIT(31) /* Enable */
1814
1815/*
1816 * Extended capability ID: 0x0010
1817 * SR-IOV
1818 */
1819#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
1820#define PCI_SRIOV_CAP_VF_MIGRATION __BIT(0)
1821#define PCI_SRIOV_CAP_ARI_CAP_HIER_PRESERVED __BIT(1)
1822#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N __BITS(31, 21)
1823#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_S 21
1824#define PCI_SRIOV_CAP_VF_MIGRATION_INTMSG_N_M 0x7ff
1825#define PCI_SRIOV_CTL 0x08 /* SR-IOV Control (16bit) */
1826#define PCI_SRIOV_CTL_VF_ENABLE __BIT(0)
1827#define PCI_SRIOV_CTL_VF_MIGRATION_SUPPORT __BIT(1)
1828#define PCI_SRIOV_CTL_VF_MIGRATION_INT_ENABLE __BIT(2)
1829#define PCI_SRIOV_CTL_VF_MSE __BIT(3)
1830#define PCI_SRIOV_CTL_ARI_CAP_HIER __BIT(4)
1831#define PCI_SRIOV_STA 0x0a /* SR-IOV Status (16bit) */
1832#define PCI_SRIOV_STA_VF_MIGRATION __BIT(0)
1833#define PCI_SRIOV_INITIAL_VFS 0x0c /* InitialVFs (16bit) */
1834#define PCI_SRIOV_TOTAL_VFS 0x0e /* TotalVFs (16bit) */
1835#define PCI_SRIOV_NUM_VFS 0x10 /* NumVFs (16bit) */
1836#define PCI_SRIOV_FUNC_DEP_LINK 0x12 /* Function Dependency Link (16bit) */
1837#define PCI_SRIOV_VF_OFF 0x14 /* First VF Offset (16bit) */
1838#define PCI_SRIOV_VF_STRIDE 0x16 /* VF Stride (16bit) */
1839#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID (16bit) */
1840#define PCI_SRIOV_PAGE_CAP 0x1c /* Supported Page Sizes */
1841#define PCI_SRIOV_PAGE_SIZE 0x20 /* System Page Size */
1842#define PCI_SRIOV_BASE_PAGE_SHIFT 12
1843#define PCI_SRIOV_BARS 0x24 /* VF BAR0-5 */
1844#define PCI_SRIOV_BAR(x) (PCI_SRIOV_BARS + ((x) * 4))
1845#define PCI_SRIOV_VF_MIG_STA_AR 0x3c /* VF Migration State Array Offset */
1846#define PCI_SRIOV_VF_MIG_STA_OFFSET __BITS(31, 3)
1847#define PCI_SRIOV_VF_MIG_STA_OFFSET_S 3
1848#define PCI_SRIOV_VF_MIG_STA_OFFSET_M 0x1fffffff
1849#define PCI_SRIOV_VF_MIG_STA_BIR __BITS(2, 0)
1850#define PCI_SRIOV_VF_MIG_STA_BIR_S 0
1851#define PCI_SRIOV_VF_MIG_STA_BIR_M 0x7
1852
1853/*
1854 * Extended capability ID: 0x0011
1855 * Multiple Root IO Virtualization
1856 */
1857
1858/*
1859 * Extended capability ID: 0x0012
1860 * Multicast
1861 */
1862#define PCI_MCAST_CAP 0x04 /* Capability Register */
1863#define PCI_MCAST_CAP_MAXGRP __BITS(5, 0) /* Max Group */
1864#define PCI_MCAST_CAP_WINSIZEREQ __BITS(13, 8) /* Window Size Requested */
1865#define PCI_MCAST_CAP_ECRCREGEN __BIT(15) /* ECRC Regen. Supported */
1866#define PCI_MCAST_CTL 0x04 /* Control Register */
1867#define PCI_MCAST_CTL_NUMGRP __BITS(5+16, 16) /* Num Group */
1868#define PCI_MCAST_CTL_ENA __BIT(15+16) /* Enable */
1869#define PCI_MCAST_BARL 0x08 /* Base Address Register (low) */
1870#define PCI_MCAST_BARL_INDPOS __BITS(5, 0) /* Index Position */
1871#define PCI_MCAST_BARL_ADDR __BITS(31, 12) /* Base Address Register(low)*/
1872#define PCI_MCAST_BARH 0x0c /* Base Address Register (high) */
1873#define PCI_MCAST_RECVL 0x10 /* Receive Register (low) */
1874#define PCI_MCAST_RECVH 0x14 /* Receive Register (high) */
1875#define PCI_MCAST_BLOCKALLL 0x18 /* Block All Register (low) */
1876#define PCI_MCAST_BLOCKALLH 0x1c /* Block All Register (high) */
1877#define PCI_MCAST_BLOCKUNTRNSL 0x20 /* Block Untranslated Register (low) */
1878#define PCI_MCAST_BLOCKUNTRNSH 0x24 /* Block Untranslated Register (high) */
1879#define PCI_MCAST_OVERLAYL 0x28 /* Overlay BAR (low) */
1880#define PCI_MCAST_OVERLAYL_SIZE __BITS(5, 0) /* Overlay Size */
1881#define PCI_MCAST_OVERLAYL_ADDR __BITS(31, 6) /* Overlay BAR (low) */
1882#define PCI_MCAST_OVERLAYH 0x2c /* Overlay BAR (high) */
1883
1884/*
1885 * Extended capability ID: 0x0013
1886 * Page Request
1887 */
1888#define PCI_PAGE_REQ_CTL 0x04 /* Control Register */
1889#define PCI_PAGE_REQ_CTL_E __BIT(0) /* Enalbe */
1890#define PCI_PAGE_REQ_CTL_R __BIT(1) /* Reset */
1891#define PCI_PAGE_REQ_STA 0x04 /* Status Register */
1892#define PCI_PAGE_REQ_STA_RF __BIT(0+16) /* Response Failure */
1893#define PCI_PAGE_REQ_STA_UPRGI __BIT(1+16) /* Unexpected Page Req Grp Idx */
1894#define PCI_PAGE_REQ_STA_S __BIT(8+16) /* Stopped */
1895#define PCI_PAGE_REQ_STA_PASIDR __BIT(15+16) /* PRG Response PASID Required */
1896#define PCI_PAGE_REQ_OUTSTCAPA 0x08 /* Outstanding Page Request Capacity */
1897#define PCI_PAGE_REQ_OUTSTALLOC 0x0c /* Outstanding Page Request Allocation */
1898
1899/*
1900 * Extended capability ID: 0x0014
1901 * Enhanced Allocation
1902 */
1903#define PCI_EA_CAP1 0x00 /* Capability First */
1904#define PCI_EA_CAP1_NUMENTRIES __BITS(21, 16) /* Num Entries */
1905#define PCI_EA_CAP2 0x04 /* Capability Second (for type1) */
1906#define PCI_EA_CAP2_SECONDARY __BITS(7, 0) /* Fixed Secondary Bus No. */
1907#define PCI_EA_CAP2_SUBORDINATE __BITS(15, 8) /* Fixed Subordinate Bus No. */
1908
1909/* Bit definitions for the first DW of each entry */
1910#define PCI_EA_ES __BITS(2, 0) /* Entry Size */
1911#define PCI_EA_BEI __BITS(7, 4) /* BAR Equivalent Indicator */
1912#define PCI_EA_BEI_BAR0 0 /* BAR0 (10h) */
1913#define PCI_EA_BEI_BAR1 1 /* BAR1 (14h) */
1914#define PCI_EA_BEI_BAR2 2 /* BAR2 (18h) */
1915#define PCI_EA_BEI_BAR3 3 /* BAR3 (1ch) */
1916#define PCI_EA_BEI_BAR4 4 /* BAR4 (20h) */
1917#define PCI_EA_BEI_BAR5 5 /* BAR5 (24h) */
1918#define PCI_EA_BEI_BEHIND 6 /* Behind the function (for type1) */
1919#define PCI_EA_BEI_NOTIND 7 /* Not Indicated */
1920#define PCI_EA_BEI_EXPROM 8 /* Expansion ROM */
1921#define PCI_EA_BEI_VFBAR0 9 /* VF BAR0 */
1922#define PCI_EA_BEI_VFBAR1 10 /* VF BAR1 */
1923#define PCI_EA_BEI_VFBAR2 11 /* VF BAR2 */
1924#define PCI_EA_BEI_VFBAR3 12 /* VF BAR3 */
1925#define PCI_EA_BEI_VFBAR4 13 /* VF BAR4 */
1926#define PCI_EA_BEI_VFBAR5 14 /* VF BAR5 */
1927#define PCI_EA_BEI_RESERVED 15 /* Reserved (treat as Not Indicated) */
1928
1929#define PCI_EA_PP __BITS(15, 8) /* Primary Properties */
1930#define PCI_EA_SP __BITS(23, 16) /* Secondary Properties */
1931/* PP and SP's values */
1932#define PCI_EA_PROP_MEM_NONPREF 0x00 /* Memory Space, Non-Prefetchable */
1933#define PCI_EA_PROP_MEM_PREF 0x01 /* Memory Space, Prefetchable */
1934#define PCI_EA_PROP_IO 0x02 /* I/O Space */
1935#define PCI_EA_PROP_VF_MEM_NONPREF 0x03 /* Resorce for VF use. Mem. Non-Pref */
1936#define PCI_EA_PROP_VF_MEM_PREF 0x04 /* Resorce for VF use. Mem. Prefetch */
1937#define PCI_EA_PROP_BB_MEM_NONPREF 0x05 /* Behind Bridge: MEM. Non-Pref */
1938#define PCI_EA_PROP_BB_MEM_PREF 0x06 /* Behind Bridge: MEM. Prefetch */
1939#define PCI_EA_PROP_BB_IO 0x07 /* Behind Bridge: I/O Space */
1940#define PCI_EA_PROP_MEM_UNAVAIL 0xfd /* Memory Space Unavailable */
1941#define PCI_EA_PROP_IO_UNAVAIL 0xfe /* IO Space Unavailable */
1942#define PCI_EA_PROP_UNAVAIL 0xff /* Entry Unavailable for use */
1943
1944#define PCI_EA_W __BIT(30) /* Writable */
1945#define PCI_EA_E __BIT(31) /* Enable for this entry */
1946
1947#define PCI_EA_LOWMASK __BITS(31, 2) /* Low register's mask */
1948#define PCI_EA_BASEMAXOFFSET_S __BIT(1) /* Field Size */
1949#define PCI_EA_BASEMAXOFFSET_64BIT __BIT(1) /* 64bit */
1950#define PCI_EA_BASEMAXOFFSET_32BIT 0 /* 32bit */
1951
1952/*
1953 * Extended capability ID: 0x0015
1954 * Resizable BAR
1955 */
1956#define PCI_RESIZBAR_CAP0 0x04 /* Capability Register(0) */
1957#define PCI_RESIZBAR_CAP(x) (PCI_RESIZBAR_CAP0 + ((x) * 8))
1958#define PCI_RESIZBAR_CAP_SIZEMASK __BITS(23, 4) /* BAR size bitmask */
1959#define PCI_RESIZBAR_CTL0 0x08 /* Control Register(0) */
1960#define PCI_RESIZBAR_CTL(x) (PCI_RESIZBAR_CTL0 + ((x) * 8))
1961#define PCI_RESIZBAR_CTL_BARIDX __BITS(2, 0)
1962#define PCI_RESIZBAR_CTL_NUMBAR __BITS(7, 5)
1963#define PCI_RESIZBAR_CTL_BARSIZ __BITS(12, 8)
1964
1965/*
1966 * Extended capability ID: 0x0016
1967 * Dynamic Power Allocation
1968 */
1969#define PCI_DPA_CAP 0x04 /* Capability */
1970#define PCI_DPA_CAP_SUBSTMAX __BITS(4, 0) /* Substate Max */
1971#define PCI_DPA_CAP_TLUINT __BITS(9, 8) /* Transition Latency Unit */
1972#define PCI_DPA_CAP_PAS __BITS(13, 12) /* Power Allocation Scale */
1973#define PCI_DPA_CAP_XLCY0 __BITS(23, 16) /* Transition Latency Value0 */
1974#define PCI_DPA_CAP_XLCY1 __BITS(31, 24) /* Transition Latency Value1 */
1975#define PCI_DPA_LATIND 0x08 /* Latency Indicator */
1976#define PCI_DPA_CS 0x0c /* Control and Status */
1977#define PCI_DPA_CS_SUBSTSTAT __BITS(4, 0) /* Substate Status */
1978#define PCI_DPA_CS_SUBSTCTLEN __BIT(8) /* Substate Control Enabled */
1979#define PCI_DPA_CS_SUBSTCTL __BITS(20, 16) /* Substate Control */
1980#define PCI_DPA_PWRALLOC 0x10 /* Start address of Power Allocation Array */
1981#define PCI_DPA_SUBST_MAXNUM 32 /* Max number of Substates (0 to 31) */
1982
1983/*
1984 * Extended capability ID: 0x0017
1985 * TPH Requester
1986 */
1987#define PCI_TPH_REQ_CAP 0x04 /* TPH Requester Capability */
1988#define PCI_TPH_REQ_CAP_NOST __BIT(0) /* No ST Mode Supported */
1989#define PCI_TPH_REQ_CAP_INTVEC __BIT(1) /* Intr Vec Mode Supported */
1990#define PCI_TPH_REQ_CAP_DEVSPEC __BIT(2) /* Device Specific Mode Supported */
1991#define PCI_TPH_REQ_CAP_XTPHREQ __BIT(8) /* Extend TPH Reqester Supported */
1992#define PCI_TPH_REQ_CAP_STTBLLOC __BITS(10, 9) /* ST Table Location */
1993#define PCI_TPH_REQ_STTBLLOC_NONE 0 /* not present */
1994#define PCI_TPH_REQ_STTBLLOC_TPHREQ 1 /* in the TPHREQ cap */
1995#define PCI_TPH_REQ_STTBLLOC_MSIX 2 /* in the MSI-X table */
1996#define PCI_TPH_REQ_CAP_STTBLSIZ __BITS(26, 16) /* ST Table Size */
1997#define PCI_TPH_REQ_CTL 0x08 /* TPH Requester Control */
1998#define PCI_TPH_REQ_CTL_STSEL __BITS(2, 0) /* ST Mode Select */
1999#define PCI_TPH_REQ_CTL_STSEL_NO 0 /* No ST Mode */
2000#define PCI_TPH_REQ_CTL_STSEL_IV 1 /* Interrupt Vector Mode */
2001#define PCI_TPH_REQ_CTL_STSEL_DS 2 /* Device Specific Mode */
2002#define PCI_TPH_REQ_CTL_TPHREQEN __BITS(9, 8) /* TPH Requester Enable */
2003#define PCI_TPH_REQ_CTL_TPHREQEN_NO 0 /* Not permitted */
2004#define PCI_TPH_REQ_CTL_TPHREQEN_TPH 1 /* TPH and no extended TPH */
2005#define PCI_TPH_REQ_CTL_TPHREQEN_RSVD 2 /* Reserved */
2006#define PCI_TPH_REQ_CTL_TPHREQEN_ETPH 3 /* TPH and Extended TPH */
2007#define PCI_TPH_REQ_STTBL 0x0c /* TPH ST Table */
2008
2009/*
2010 * Extended capability ID: 0x0018
2011 * Latency Tolerance Reporting
2012 */
2013#define PCI_LTR_MAXSNOOPLAT 0x04 /* Max Snoop Latency */
2014#define PCI_LTR_MAXSNOOPLAT_VAL __BITS(9, 0) /* Max Snoop LatencyValue */
2015#define PCI_LTR_MAXSNOOPLAT_SCALE __BITS(12, 10) /* Max Snoop LatencyScale */
2016#define PCI_LTR_MAXNOSNOOPLAT 0x04 /* Max No-Snoop Latency */
2017#define PCI_LTR_MAXNOSNOOPLAT_VAL __BITS(25, 16) /* Max No-Snoop LatencyValue*/
2018#define PCI_LTR_MAXNOSNOOPLAT_SCALE __BITS(28, 26) /*Max NoSnoop LatencyScale*/
2019#define PCI_LTR_SCALETONS(x) (1 << ((x) * 5))
2020
2021/*
2022 * Extended capability ID: 0x0019
2023 * Seconday PCI Express Extended Capability
2024 */
2025#define PCI_SECPCIE_LCTL3 0x04 /* Link Control 3 */
2026#define PCI_SECPCIE_LCTL3_PERFEQ __BIT(0) /* Perform Equalization */
2027#define PCI_SECPCIE_LCTL3_LINKEQREQ_IE __BIT(1) /* Link Eq. Req. Int. Ena. */
2028#define PCI_SECPCIE_LCTL3_ELSKPOSGENV __BITS(15, 9) /* En. Lo. SKP OS Gen V*/
2029#define PCI_SECPCIE_LANEERR_STA 0x08 /* Lane Error Status */
2030#define PCI_SECPCIE_EQCTLS 0x0c /* Equalization Control [0-maxlane] */
2031#define PCI_SECPCIE_EQCTL(x) (PCI_SECPCIE_EQCTLS + ((x) * 2))
2032#define PCI_SECPCIE_EQCTL_DP_XMIT_PRESET __BITS(3, 0) /* DwnStPort Xmit Pres */
2033#define PCI_SECPCIE_EQCTL_DP_RCV_HINT __BITS(6, 4) /* DwnStPort Rcv PreHnt */
2034#define PCI_SECPCIE_EQCTL_UP_XMIT_PRESET __BITS(11, 8) /* UpStPort Xmit Pres */
2035#define PCI_SECPCIE_EQCTL_UP_RCV_HINT __BITS(14, 12) /* UpStPort Rcv PreHnt*/
2036
2037/*
2038 * Extended capability ID: 0x001a
2039 * Protocol Multiplexing
2040 */
2041
2042/*
2043 * Extended capability ID: 0x001b
2044 * Process Address Space ID
2045 */
2046#define PCI_PASID_CAP 0x04 /* Capability Register */
2047#define PCI_PASID_CAP_XPERM __BIT(1) /* Execute Permission Supported */
2048#define PCI_PASID_CAP_PRIVMODE __BIT(2) /* Privileged Mode Supported */
2049#define PCI_PASID_CAP_MAXPASIDW __BITS(12, 8) /* Max PASID Width */
2050#define PCI_PASID_CTL 0x04 /* Control Register */
2051#define PCI_PASID_CTL_PASID_EN __BIT(0+16) /* PASID Enable */
2052#define PCI_PASID_CTL_XPERM_EN __BIT(1+16) /* Execute Permission Enable */
2053#define PCI_PASID_CTL_PRIVMODE_EN __BIT(2+16) /* Privileged Mode Enable */
2054
2055/*
2056 * Extended capability ID: 0x001c
2057 * LN Requester
2058 */
2059#define PCI_LNR_CAP 0x04 /* Capability Register */
2060#define PCI_LNR_CAP_64 __BIT(0) /* LNR-64 Supported */
2061#define PCI_LNR_CAP_128 __BIT(1) /* LNR-128 Supported */
2062#define PCI_LNR_CAP_REGISTMAX __BITS(12, 8) /* LNR Registration MAX */
2063#define PCI_LNR_CTL 0x04 /* Control Register */
2064#define PCI_LNR_CTL_EN __BIT(0+16) /* LNR Enable */
2065#define PCI_LNR_CTL_CLS __BIT(1+16) /* LNR CLS */
2066#define PCI_LNR_CTL_REGISTLIM __BITS(28, 24) /* LNR Registration Limit */
2067
2068/*
2069 * Extended capability ID: 0x001d
2070 * Downstream Port Containment
2071 */
2072
2073#define PCI_DPC_CCR 0x04 /* Capability and Control Register */
2074#define PCI_DPCCAP_IMSGN __BITS(4, 0) /* Interrupt Message Number */
2075#define PCI_DPCCAP_RPEXT __BIT(5) /* RP Extensions for DPC */
2076#define PCI_DPCCAP_POISONTLPEB __BIT(6) /* Poisoned TLP Egress Blckng.*/
2077#define PCI_DPCCAP_SWTRIG __BIT(7) /* DPC Software Triggering */
2078#define PCI_DPCCAP_RPPIOLOGSZ __BITS(11, 8) /* RP PIO Log Size */
2079#define PCI_DPCCAP_DLACTECORS __BIT(12) /* DL_Active ERR_COR Signaling*/
2080#define PCI_DPCCTL_TIRGEN __BITS(17, 16) /* DPC Trigger Enable */
2081#define PCI_DPCCTL_COMPCTL __BIT(18) /* DPC Completion Control */
2082#define PCI_DPCCTL_IE __BIT(19) /* DPC Interrupt Enable */
2083#define PCI_DPCCTL_ERRCOREN __BIT(20) /* DPC ERR_COR enable */
2084#define PCI_DPCCTL_POISONTLPEB __BIT(21) /* Poisoned TLP Egress Blckng.*/
2085#define PCI_DPCCTL_SWTRIG __BIT(22) /* DPC Software Trigger */
2086#define PCI_DPCCTL_DLACTECOR __BIT(23) /* DL_Active ERR_COR Enable */
2087
2088#define PCI_DPC_STATESID 0x08 /* Status and Error Source ID Register */
2089#define PCI_DPCSTAT_TSTAT __BIT(0) /* DPC Trigger Staus */
2090#define PCI_DPCSTAT_TREASON __BITS(2, 1) /* DPC Trigger Reason */
2091#define PCI_DPCSTAT_ISTAT __BIT(3) /* DPC Interrupt Status */
2092#define PCI_DPCSTAT_RPBUSY __BIT(4) /* DPC RP Busy */
2093#define PCI_DPCSTAT_TRIGREXT __BITS(6, 5) /* DPC Trigger Reason Extntn. */
2094#define PCI_DPCSTAT_RPPIOFEP __BITS(12, 8) /* RP PIO First Error Pointer */
2095#define PCI_DPCESID __BITS(31, 16) /* DPC Error Source ID */
2096
2097#define PCI_DPC_RPPIO_STAT 0x0c /* RP PIO Status Register */
2098#define PCI_DPC_RPPIO_CFGUR_CPL __BIT(0) /* CfgReq received UR Complt. */
2099#define PCI_DPC_RPPIO_CFGCA_CPL __BIT(1) /* CfgReq received CA Complt. */
2100#define PCI_DPC_RPPIO_CFG_CTO __BIT(2) /* CfgReq Completion Timeout */
2101#define PCI_DPC_RPPIO_IOUR_CPL __BIT(8) /* I/OReq received UR Complt. */
2102#define PCI_DPC_RPPIO_IOCA_CPL __BIT(9) /* I/OReq received CA Complt. */
2103#define PCI_DPC_RPPIO_IO_CTO __BIT(10) /* I/OReq Completion Timeout */
2104#define PCI_DPC_RPPIO_MEMUR_CPL __BIT(16) /* MemReq received UR Complt. */
2105#define PCI_DPC_RPPIO_MEMCA_CPL __BIT(17) /* MemReq received CA Complt. */
2106#define PCI_DPC_RPPIO_MEM_CTO __BIT(18) /* MemReq Completion Timeout */
2107
2108#define PCI_DPC_RPPIO_MASK 0x10 /* RP PIO Mask Register */
2109 /* Bits are the same as RP PIO Status Register */
2110#define PCI_DPC_RPPIO_SEVE 0x14 /* RP PIO Severity Register */
2111 /* Same */
2112#define PCI_DPC_RPPIO_SYSERR 0x18 /* RP PIO SysError Register */
2113 /* Same */
2114#define PCI_DPC_RPPIO_EXCPT 0x1c /* RP PIO Exception Register */
2115 /* Same */
2116#define PCI_DPC_RPPIO_HLOG 0x20 /* RP PIO Header Log Register */
2117#define PCI_DPC_RPPIO_IMPSLOG 0x30 /* RP PIO ImpSpec Log Register */
2118#define PCI_DPC_RPPIO_TLPPLOG 0x34 /* RP PIO TLP Prefix Log Register */
2119
2120/*
2121 * Extended capability ID: 0x001e
2122 * L1 PM Substates
2123 */
2124#define PCI_L1PM_CAP 0x04 /* Capabilities Register */
2125#define PCI_L1PM_CAP_PCIPM12 __BIT(0) /* PCI-PM L1.2 Supported */
2126#define PCI_L1PM_CAP_PCIPM11 __BIT(1) /* PCI-PM L1.1 Supported */
2127#define PCI_L1PM_CAP_ASPM12 __BIT(2) /* ASPM L1.2 Supported */
2128#define PCI_L1PM_CAP_ASPM11 __BIT(3) /* ASPM L1.1 Supported */
2129#define PCI_L1PM_CAP_L1PM __BIT(4) /* L1 PM Substates Supported */
2130#define PCI_L1PM_CAP_LA __BIT(5) /* Link Activation Supported */
2131#define PCI_L1PM_CAP_PCMRT __BITS(15, 8) /*Port Common Mode Restore Time*/
2132#define PCI_L1PM_CAP_PTPOSCALE __BITS(17, 16) /* Port T_POWER_ON Scale */
2133#define PCI_L1PM_CAP_PTPOVAL __BITS(23, 19) /* Port T_POWER_ON Value */
2134#define PCI_L1PM_CTL1 0x08 /* Control Register 1 */
2135#define PCI_L1PM_CTL1_PCIPM12_EN __BIT(0) /* PCI-PM L1.2 Enable */
2136#define PCI_L1PM_CTL1_PCIPM11_EN __BIT(1) /* PCI-PM L1.1 Enable */
2137#define PCI_L1PM_CTL1_ASPM12_EN __BIT(2) /* ASPM L1.2 Enable */
2138#define PCI_L1PM_CTL1_ASPM11_EN __BIT(3) /* ASPM L1.1 Enable */
2139#define PCI_L1PM_CTL1_LAIE __BIT(4) /* Link Activation Int. En. */
2140#define PCI_L1PM_CTL1_LA __BIT(5) /* Link Activation Control */
2141#define PCI_L1PM_CTL1_CMRT __BITS(15, 8) /* Common Mode Restore Time */
2142#define PCI_L1PM_CTL1_LTRTHVAL __BITS(25, 16) /* LTR L1.2 THRESHOLD Value */
2143#define PCI_L1PM_CTL1_LTRTHSCALE __BITS(31, 29) /* LTR L1.2 THRESHOLD Scale */
2144#define PCI_L1PM_CTL2 0x0c /* Control Register 2 */
2145#define PCI_L1PM_CTL2_TPOSCALE __BITS(1, 0) /* T_POWER_ON Scale */
2146#define PCI_L1PM_CTL2_TPOVAL __BITS(7, 3) /* T_POWER_ON Value */
2147#define PCI_L1PM_STAT 0x10 /* Status Register */
2148#define PCI_L1PM_STAT_LA __BIT(0) /* Link Activation Status */
2149
2150/*
2151 * Extended capability ID: 0x001f
2152 * Precision Time Management
2153 */
2154#define PCI_PTM_CAP 0x04 /* Capabilities Register */
2155#define PCI_PTM_CAP_REQ __BIT(0) /* PTM Requester Capable */
2156#define PCI_PTM_CAP_RESP __BIT(1) /* PTM Responder Capable */
2157#define PCI_PTM_CAP_ROOT __BIT(2) /* PTM Root Capable */
2158#define PCI_PTM_CAP_LCLCLKGRNL __BITS(15, 8) /* Local Clock Granularity */
2159#define PCI_PTM_CTL 0x08 /* Control Register */
2160#define PCI_PTM_CTL_EN __BIT(0) /* PTM Enable */
2161#define PCI_PTM_CTL_ROOTSEL __BIT(1) /* Root Select */
2162#define PCI_PTM_CTL_EFCTGRNL __BITS(15, 8) /* Effective Granularity */
2163
2164/*
2165 * Extended capability ID: 0x0020
2166 * M-PCIe
2167 */
2168
2169/*
2170 * Extended capability ID: 0x0021
2171 * Function Reading Status Queueing
2172 */
2173
2174/*
2175 * Extended capability ID: 0x0022
2176 * Readiness Time Reporting
2177 */
2178
2179/*
2180 * Extended capability ID: 0x0023
2181 * Designated Vendor-Specific
2182 */
2183
2184/*
2185 * Extended capability ID: 0x0024
2186 * VF Resizable BAR
2187 */
2188
2189/*
2190 * Extended capability ID: 0x0028
2191 * Hierarchy ID
2192 */
2193
2194/*
2195 * Extended capability ID: 0x0029
2196 * Native PCIe Enclosure Management
2197 */
2198
2199#endif /* _DEV_PCI_PCIREG_H_ */
2200