1/* $NetBSD: pccbbreg.h,v 1.15 2009/12/15 22:17:12 snj Exp $ */
2
3/*
4 * Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#ifndef _DEV_PCI_PCCBBREG_H_
28#define _DEV_PCI_PCCBBREG_H_
29
30
31
32
33#define PCI_SOCKBASE 0x10 /* Socket Base Address Register */
34#define PCI_CBB_SECSTATUS 0x14 /* secondary status (starts at 0x16) */
35#define PCI_BUSNUM 0x18 /* latency timer, Subordinate bus number */
36#define PCI_LEGACY 0x44 /* legacy IO register address (32 bits) */
37#define PCI_SYSCTRL 0x80 /* System control */
38#define PCI_CBCTRL 0x90 /* Retry status, Card ctrl, Device ctrl */
39
40#define PCI_CLASS_INTERFACE_MASK 0xffffff00
41#define PCI_CLASS_INTERFACE_YENTA 0x06070000
42
43#define CBB_SECSTATUS_CBMABORT 0x20000000
44
45#define CB_SOCKET_EVENT 0x00 /* offset of cardbus socket event reg */
46#define CB_SOCKET_MASK 0x04 /* offset of cardbus socket mask register */
47#define CB_SOCKET_STAT 0x08 /* offset of cardbus socket present-state */
48#define CB_SOCKET_FORCE 0x0c /* offset of cardbus socket force event */
49#define CB_SOCKET_CTRL 0x10 /* offset of cardbus socket control reg */
50
51#define PCCBB_SOCKEVENT_BITS "\020\001CSTS\002CD1\003CD2\004PWR"
52#define PCCBB_SOCKSTATE_BITS "\020\001CSTS\002CD1\003CD3\004PWR" \
53 "\00516BIT\006CB\007CINT\010NOTA\011DLOST\012BADVCC" \
54 "\0135v\0143v\015Xv\016Yv\0355vS\0363vS\037XvS\040YvS"
55
56/* CardBus latency timer, Subordinate bus no, CardBus bus no and PCI bus no */
57#define PCI_CB_LSCP_REG 0x18
58/* CardBus memory and io windows */
59#define PCI_CB_MEMBASE0 0x1c
60#define PCI_CB_MEMLIMIT0 0x20
61#define PCI_CB_MEMBASE1 0x24
62#define PCI_CB_MEMLIMIT1 0x28
63#define PCI_CB_IOBASE0 0x2c
64#define PCI_CB_IOLIMIT0 0x30
65#define PCI_CB_IOBASE1 0x34
66#define PCI_CB_IOLIMIT1 0x38
67
68/* PCI_CB_LSCP_REG */
69#define PCI_CB_LATENCY_SHIFT 24
70#define PCI_CB_LATENCY_MASK 0xff
71#define PCI_CB_LATENCY(x) (((x) >> PCI_CB_LATENCY_SHIFT) & PCI_CB_LATENCY_MASK)
72
73
74
75/* PCI_BCR_INTR bits for generic PCI-CardBus bridge */
76#define CB_BCR_RESET_ENABLE 0x00400000
77#define CB_BCR_INTR_IREQ_ENABLE 0x00800000
78#define CB_BCR_PREFETCH_MEMWIN0 0x01000000
79#define CB_BCR_PREFETCH_MEMWIN1 0x02000000
80#define CB_BCR_WRITE_POST_ENABLE 0x04000000
81
82/* TI [14][245]xx */
83#define PCI12XX_MMCTRL 0x84
84
85/* TI 12xx/14xx/15xx (except 1250, 1251, 1251B/1450) */
86#define PCI12XX_MFUNC 0x8c
87#define PCI12XX_MFUNC_PIN0 0x0000000f
88#define PCI12XX_MFUNC_PIN0_INTA 0x02
89#define PCI12XX_MFUNC_PIN1 0x000000f0
90#define PCI12XX_MFUNC_PIN1_INTB 0x20
91#define PCI12XX_MFUNC_PIN2 0x00000f00
92#define PCI12XX_MFUNC_PIN3 0x0000f000
93#define PCI12XX_MFUNC_PIN4 0x000f0000
94#define PCI12XX_MFUNC_PIN5 0x00f00000
95#define PCI12XX_MFUNC_PIN6 0x0f000000
96
97/* PCI_CBCTRL bits for TI PCI113X */
98#define PCI113X_CBCTRL_INT_SERIAL 0x040000
99#define PCI113X_CBCTRL_INT_ISA 0x020000
100#define PCI113X_CBCTRL_INT_MASK 0x060000
101#define PCI113X_CBCTRL_RIENB 0x8000 /* Ring indicate output enable */
102#define PCI113X_CBCTRL_ZVENAB 0x4000 /* ZV mode enable */
103#define PCI113X_CBCTRL_PCI_IRQ_ENA 0x2000 /* PCI intr enable (funct and CSC) */
104#define PCI113X_CBCTRL_PCI_INTR 0x1000 /* PCI functional intr req */
105#define PCI113X_CBCTRL_PCI_CSC 0x0800 /* CSC intr route to PCI */
106#define PCI113X_CBCTRL_PCI_CSC_D 0x0400 /* unknown */
107#define PCI113X_CBCTRL_SPK_ENA 0x0200 /* Speaker enable */
108#define PCI113X_CBCTRL_INTR_DET 0x0100 /* functional interrupt detect */
109
110/* PCI_CBCTRL bits for TI PCI12XX */
111#define PCI12XX_SYSCTRL_INTRTIE 0x20000000u
112#define PCI12XX_SYSCTRL_VCCPROT 0x200000
113#define PCI12XX_SYSCTRL_PWRSAVE 0x000040
114#define PCI12XX_SYSCTRL_SUBSYSRW 0x000020
115#define PCI12XX_SYSCTRL_CB_DPAR 0x000010
116#define PCI12XX_SYSCTRL_CDMA_EN 0x000008
117#define PCI12XX_SYSCTRL_KEEPCLK 0x000002
118#define PCI12XX_SYSCTRL_RIMUX 0x000001
119#define PCI12XX_CBCTRL_CSC 0x20000000u
120#define PCI12XX_CBCTRL_ASYNC_CSC 0x01000000u
121#define PCI12XX_CBCTRL_INT_SERIAL 0x060000
122#define PCI12XX_CBCTRL_INT_PCI_SERIAL 0x040000
123#define PCI12XX_CBCTRL_INT_ISA 0x020000
124#define PCI12XX_CBCTRL_INT_PCI 0x000000
125#define PCI12XX_CBCTRL_INT_MASK 0x060000
126#define PCI12XX_CBCTRL_RIENB 0x8000 /* Ring indicate output enable */
127#define PCI12XX_CBCTRL_ZVENAB 0x4000 /* ZV mode enable */
128#define PCI12XX_CBCTRL_AUD2MUX 0x0400 /* unknown */
129#define PCI12XX_CBCTRL_SPK_ENA 0x0200 /* Speaker enable */
130#define PCI12XX_CBCTRL_INTR_DET 0x0100 /* functional interrupt detect */
131
132/* 1: permit burst read from CardBus (default: on) */
133#define PCI1420_SYSCTRL_MRBURSTDN __BIT(15)
134/* 1: permit burst read from PCI bus (default: off!) */
135#define PCI1420_SYSCTRL_MRBURSTUP __BIT(14)
136
137#define PCI1420_SYSCTRL_MRBURST \
138 (PCI1420_SYSCTRL_MRBURSTDN|PCI1420_SYSCTRL_MRBURSTUP)
139
140/* PCI_BCR_INTR additional bit for Rx5C46[567] */
141#define CB_BCRI_RL_3E0_ENA 0x08000000
142#define CB_BCRI_RL_3E2_ENA 0x10000000
143
144
145/* PCI configuration register definition for Ricoh 5C475 */
146#define RICOH_PCI_MISC_CTRL 0x82
147
148
149/*
150 * Special resister definition for Toshiba ToPIC95/97
151 * These values are borrowed from pcmcia-cs/Linux.
152 */
153#define TOPIC_SOCKET_CTRL 0x90
154# define TOPIC_SOCKET_CTRL_SCR_IRQSEL 0x00000001 /* PCI intr */
155
156#define TOPIC_SLOT_CTRL 0xa0
157# define TOPIC_SLOT_CTRL_SLOTON 0x00000080
158# define TOPIC_SLOT_CTRL_SLOTEN 0x00000040
159# define TOPIC_SLOT_CTRL_ID_LOCK 0x00000020
160# define TOPIC_SLOT_CTRL_ID_WP 0x00000010
161# define TOPIC_SLOT_CTRL_PORT_MASK 0x0000000c
162# define TOPIC_SLOT_CTRL_PORT_SHIFT 2
163# define TOPIC_SLOT_CTRL_OSF_MASK 0x00000003
164# define TOPIC_SLOT_CTRL_OSF_SHIFT 0
165
166# define TOPIC_SLOT_CTRL_INTB 0x00002000
167# define TOPIC_SLOT_CTRL_INTA 0x00001000
168# define TOPIC_SLOT_CTRL_INT_MASK 0x00003000
169# define TOPIC_SLOT_CTRL_CLOCK_MASK 0x00000c00
170# define TOPIC_SLOT_CTRL_CLOCK_2 0x00000800 /* PCI Clock/2 */
171# define TOPIC_SLOT_CTRL_CLOCK_1 0x00000400 /* PCI Clock */
172# define TOPIC_SLOT_CTRL_CLOCK_0 0x00000000 /* no clock */
173# define TOPIC97_SLOT_CTRL_STSIRQP 0x00000400 /* status change intr pulse */
174# define TOPIC97_SLOT_CTRL_IRQP 0x00000200 /* function intr pulse */
175# define TOPIC97_SLOT_CTRL_PCIINT 0x00000100 /* intr routing to PCI INT */
176
177# define TOPIC_SLOT_CTRL_CARDBUS 0x80000000
178# define TOPIC_SLOT_CTRL_VS1 0x04000000
179# define TOPIC_SLOT_CTRL_VS2 0x02000000
180# define TOPIC_SLOT_CTRL_SWDETECT 0x01000000
181
182#define TOPIC_REG_CTRL 0x00a4
183# define TOPIC_REG_CTRL_RESUME_RESET 0x80000000
184# define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000
185# define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000
186# define TOPIC97_REG_CTRL_TESTMODE 0x10000000
187# define TOPIC97_REG_CTRL_IOPLUP 0x08000000
188# define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000
189# define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000
190# define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000f800
191# define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11
192# define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004
193# define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002
194# define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001
195
196
197
198/* socket event register (CB_SOCKET_EVENT) elements */
199#define CB_SOCKET_EVENT_CSTS 0x01 /* CARDSTS event occurs */
200#define CB_SOCKET_EVENT_CD 0x06 /* CD event occurs */
201#define CB_SOCKET_EVENT_CD1 0x02 /* CD1 event occurs */
202#define CB_SOCKET_EVENT_CD2 0x04 /* CD2 event occurs */
203#define CB_SOCKET_EVENT_POWER 0x08 /* Power cycle event occurs */
204
205
206/* socket mask register (CB_SOCKET_MASK) elements */
207#define CB_SOCKET_MASK_CSTS 0x01 /* CARDSTS event mask */
208#define CB_SOCKET_MASK_CD 0x06 /* CD event mask */
209#define CB_SOCKET_MASK_POWER 0x08 /* Power cycle event mask */
210
211/* socket present-state register (CB_SOCKET_STAT) elements */
212#define CB_SOCKET_STAT_CARDSTS 0x01 /* card status change bit */
213#define CB_SOCKET_STAT_CD1 0x02 /* card detect 1 */
214#define CB_SOCKET_STAT_CD2 0x04 /* card detect 2 */
215#define CB_SOCKET_STAT_CD 0x06 /* card detect 1 and 2 */
216#define CB_SOCKET_STAT_PWRCYCLE 0x08 /* power cycle */
217#define CB_SOCKET_STAT_16BIT 0x010 /* 16-bit card */
218#define CB_SOCKET_STAT_CB 0x020 /* cardbus card */
219#define CB_SOCKET_STAT_IREQ 0x040 /* READY(~IREQ)//(~CINT) bit */
220#define CB_SOCKET_STAT_NOTCARD 0x080 /* Inserted card is unrecognisable */
221#define CB_SOCKET_STAT_DATALOST 0x0100 /* data lost */
222#define CB_SOCKET_STAT_BADVCC 0x0200 /* Bad Vcc Request */
223#define CB_SOCKET_STAT_5VCARD 0x0400 /* 5 V Card */
224#define CB_SOCKET_STAT_3VCARD 0x0800 /* 3.3 V Card */
225#define CB_SOCKET_STAT_XVCARD 0x01000 /* X.X V Card */
226#define CB_SOCKET_STAT_YVCARD 0x02000 /* Y.Y V Card */
227#define CB_SOCKET_STAT_5VSOCK 0x10000000 /* 5 V Socket */
228#define CB_SOCKET_STAT_3VSOCK 0x20000000 /* 3.3 V Socket */
229#define CB_SOCKET_STAT_XVSOCK 0x40000000 /* X.X V Socket */
230#define CB_SOCKET_STAT_YVSOCK 0x80000000 /* Y.Y V Socket */
231
232/* socket force event register (CB_SOCKET_FORCE) elements */
233#define CB_SOCKET_FORCE_BADVCC 0x0200 /* Bad Vcc Request */
234
235
236/* socket control register (CB_SOCKET_CTRL) elements */
237#define CB_SOCKET_CTRL_VPPMASK 0x07
238#define CB_SOCKET_CTRL_VPP_OFF 0x00
239#define CB_SOCKET_CTRL_VPP_12V 0x01
240#define CB_SOCKET_CTRL_VPP_5V 0x02
241#define CB_SOCKET_CTRL_VPP_3V 0x03
242#define CB_SOCKET_CTRL_VPP_XV 0x04
243#define CB_SOCKET_CTRL_VPP_YV 0x05
244
245#define CB_SOCKET_CTRL_VCCMASK 0x070
246#define CB_SOCKET_CTRL_VCC_OFF 0x000
247#define CB_SOCKET_CTRL_VCC_5V 0x020
248#define CB_SOCKET_CTRL_VCC_3V 0x030
249#define CB_SOCKET_CTRL_VCC_XV 0x040
250#define CB_SOCKET_CTRL_VCC_YV 0x050
251
252#define CB_SOCKET_CTRL_STOPCLK 0x080
253
254
255
256/* PCCARD VOLTAGE */
257#define PCCARD_VCC_UKN 0x00 /* unknown */
258#define PCCARD_VCC_5V 0x01
259#define PCCARD_VCC_3V 0x02
260#define PCCARD_VCC_XV 0x04
261#define PCCARD_VCC_YV 0x08
262
263
264#endif /* _DEV_PCI_PCCBBREG_H_ */
265