1/* $NetBSD: if_vmxreg.h,v 1.3 2019/03/05 08:25:02 msaitoh Exp $ */
2/* $OpenBSD: if_vmxreg.h,v 1.3 2013/08/28 10:19:19 reyk Exp $ */
3
4/*
5 * Copyright (c) 2013 Tsubai Masanari
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20struct UPT1_TxStats {
21 uint64_t TSO_packets;
22 uint64_t TSO_bytes;
23 uint64_t ucast_packets;
24 uint64_t ucast_bytes;
25 uint64_t mcast_packets;
26 uint64_t mcast_bytes;
27 uint64_t bcast_packets;
28 uint64_t bcast_bytes;
29 uint64_t error;
30 uint64_t discard;
31} __packed;
32
33struct UPT1_RxStats {
34 uint64_t LRO_packets;
35 uint64_t LRO_bytes;
36 uint64_t ucast_packets;
37 uint64_t ucast_bytes;
38 uint64_t mcast_packets;
39 uint64_t mcast_bytes;
40 uint64_t bcast_packets;
41 uint64_t bcast_bytes;
42 uint64_t nobuffer;
43 uint64_t error;
44} __packed;
45
46/* interrupt moderation levels */
47#define UPT1_IMOD_NONE 0 /* no moderation */
48#define UPT1_IMOD_HIGHEST 7 /* least interrupts */
49#define UPT1_IMOD_ADAPTIVE 8 /* adaptive interrupt moderation */
50
51/* hardware features */
52#define UPT1_F_CSUM 0x0001 /* Rx checksum verification */
53#define UPT1_F_RSS 0x0002 /* receive side scaling */
54#define UPT1_F_VLAN 0x0004 /* VLAN tag stripping */
55#define UPT1_F_LRO 0x0008 /* large receive offloading */
56
57#define VMXNET3_BAR0_IMASK(irq) (0x000 + (irq) * 8) /* interrupt mask */
58#define VMXNET3_BAR0_TXH(q) (0x600 + (q) * 8) /* Tx head */
59#define VMXNET3_BAR0_RXH1(q) (0x800 + (q) * 8) /* ring1 Rx head */
60#define VMXNET3_BAR0_RXH2(q) (0xa00 + (q) * 8) /* ring2 Rx head */
61#define VMXNET3_BAR1_VRRS 0x000 /* VMXNET3 revision report selection */
62#define VMXNET3_BAR1_UVRS 0x008 /* UPT version report selection */
63#define VMXNET3_BAR1_DSL 0x010 /* driver shared address low */
64#define VMXNET3_BAR1_DSH 0x018 /* driver shared address high */
65#define VMXNET3_BAR1_CMD 0x020 /* command */
66#define VMXNET3_BAR1_MACL 0x028 /* MAC address low */
67#define VMXNET3_BAR1_MACH 0x030 /* MAC address high */
68#define VMXNET3_BAR1_INTR 0x038 /* interrupt status */
69#define VMXNET3_BAR1_EVENT 0x040 /* event status */
70
71#define VMXNET3_CMD_ENABLE 0xcafe0000 /* enable VMXNET3 */
72#define VMXNET3_CMD_DISABLE 0xcafe0001 /* disable VMXNET3 */
73#define VMXNET3_CMD_RESET 0xcafe0002 /* reset device */
74#define VMXNET3_CMD_SET_RXMODE 0xcafe0003 /* set interface flags */
75#define VMXNET3_CMD_SET_FILTER 0xcafe0004 /* set address filter */
76#define VMXNET3_CMD_VLAN_FILTER 0xcafe0005 /* set VLAN filter */
77#define VMXNET3_CMD_GET_STATUS 0xf00d0000 /* get queue errors */
78#define VMXNET3_CMD_GET_STATS 0xf00d0001 /* get queue statistics */
79#define VMXNET3_CMD_GET_LINK 0xf00d0002 /* get link status */
80#define VMXNET3_CMD_GET_MACL 0xf00d0003
81#define VMXNET3_CMD_GET_MACH 0xf00d0004
82#define VMXNET3_CMD_GET_INTRCFG 0xf00d0008 /* get interrupt config */
83
84#define VMXNET3_DMADESC_ALIGN 128
85#define VMXNET3_INIT_GEN 1
86
87/* All descriptors are in little-endian format. */
88struct vmxnet3_txdesc {
89 uint64_t addr;
90
91 uint32_t len:14;
92 uint32_t gen:1; /* Generation */
93 uint32_t pad1:1;
94 uint32_t dtype:1; /* Descriptor type */
95 uint32_t pad2:1;
96 uint32_t offload_pos:14; /* Offloading position */
97
98 uint32_t hlen:10; /* Header len */
99 uint32_t offload_mode:2; /* Offloading mode */
100 uint32_t eop:1; /* End of packet */
101 uint32_t compreq:1; /* Completion request */
102 uint32_t pad3:1;
103 uint32_t vtag_mode:1; /* VLAN tag insertion mode */
104 uint32_t vtag:16; /* VLAN tag */
105} __packed;
106
107/* offloading modes */
108#define VMXNET3_OM_NONE 0
109#define VMXNET3_OM_CSUM 2
110#define VMXNET3_OM_TSO 3
111
112struct vmxnet3_txcompdesc {
113 uint32_t eop_idx:12; /* EOP index in Tx ring */
114 uint32_t pad1:20;
115
116 uint32_t pad2:32;
117 uint32_t pad3:32;
118
119 uint32_t rsvd:24;
120 uint32_t type:7;
121 uint32_t gen:1;
122} __packed;
123
124struct vmxnet3_rxdesc {
125 uint64_t addr;
126
127 uint32_t len:14;
128 uint32_t btype:1; /* Buffer type */
129 uint32_t dtype:1; /* Descriptor type */
130 uint32_t rsvd:15;
131 uint32_t gen:1;
132
133 uint32_t pad1:32;
134} __packed;
135
136/* buffer types */
137#define VMXNET3_BTYPE_HEAD 0 /* head only */
138#define VMXNET3_BTYPE_BODY 1 /* body only */
139
140struct vmxnet3_rxcompdesc {
141 uint32_t rxd_idx:12; /* Rx descriptor index */
142 uint32_t pad1:2;
143 uint32_t eop:1; /* End of packet */
144 uint32_t sop:1; /* Start of packet */
145 uint32_t qid:10;
146 uint32_t rss_type:4;
147 uint32_t no_csum:1; /* No checksum calculated */
148 uint32_t pad2:1;
149
150 uint32_t rss_hash:32; /* RSS hash value */
151
152 uint32_t len:14;
153 uint32_t error:1;
154 uint32_t vlan:1; /* 802.1Q VLAN frame */
155 uint32_t vtag:16; /* VLAN tag */
156
157 uint32_t csum:16;
158 uint32_t csum_ok:1; /* TCP/UDP checksum ok */
159 uint32_t udp:1;
160 uint32_t tcp:1;
161 uint32_t ipcsum_ok:1; /* IP checksum OK */
162 uint32_t ipv6:1;
163 uint32_t ipv4:1;
164 uint32_t fragment:1; /* IP fragment */
165 uint32_t fcs:1; /* Frame CRC correct */
166 uint32_t type:7;
167 uint32_t gen:1;
168} __packed;
169
170#define VMXNET3_RCD_RSS_TYPE_NONE 0
171#define VMXNET3_RCD_RSS_TYPE_IPV4 1
172#define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
173#define VMXNET3_RCD_RSS_TYPE_IPV6 3
174#define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
175
176#define VMXNET3_REV1_MAGIC 0xbabefee1
177
178#define VMXNET3_GOS_UNKNOWN 0x00
179#define VMXNET3_GOS_LINUX 0x04
180#define VMXNET3_GOS_WINDOWS 0x08
181#define VMXNET3_GOS_SOLARIS 0x0c
182#define VMXNET3_GOS_FREEBSD 0x10
183#define VMXNET3_GOS_PXE 0x14
184
185#define VMXNET3_GOS_32BIT 0x01
186#define VMXNET3_GOS_64BIT 0x02
187
188#define VMXNET3_MAX_TX_QUEUES 8
189#define VMXNET3_MAX_RX_QUEUES 16
190#define VMXNET3_MAX_INTRS (VMXNET3_MAX_TX_QUEUES + VMXNET3_MAX_RX_QUEUES + 1)
191
192#define VMXNET3_RX_INTR_INDEX 0
193#define VMXNET3_TX_INTR_INDEX 1
194#define VMXNET3_EV_INTR_INDEX 2
195
196#define VMXNET3_ICTRL_DISABLE_ALL 0x01
197
198#define VMXNET3_RXMODE_UCAST 0x01
199#define VMXNET3_RXMODE_MCAST 0x02
200#define VMXNET3_RXMODE_BCAST 0x04
201#define VMXNET3_RXMODE_ALLMULTI 0x08
202#define VMXNET3_RXMODE_PROMISC 0x10
203
204#define VMXNET3_EVENT_RQERROR 0x01
205#define VMXNET3_EVENT_TQERROR 0x02
206#define VMXNET3_EVENT_LINK 0x04
207#define VMXNET3_EVENT_DIC 0x08
208#define VMXNET3_EVENT_DEBUG 0x10
209
210#define VMXNET3_MAX_MTU 9000
211#define VMXNET3_MIN_MTU 60
212
213#define VMXNET3_IMM_AUTO 0x00
214#define VMXNET3_IMM_ACTIVE 0x01
215#define VMXNET3_IMM_LAZY 0x02
216
217#define VMXNET3_IT_AUTO 0x00
218#define VMXNET3_IT_LEGACY 0x01
219#define VMXNET3_IT_MSI 0x02
220#define VMXNET3_IT_MSIX 0x03
221
222struct vmxnet3_driver_shared {
223 uint32_t magic;
224 uint32_t pad1;
225
226 uint32_t version; /* driver version */
227 uint32_t guest; /* guest OS */
228 uint32_t vmxnet3_revision; /* supported VMXNET3 revision */
229 uint32_t upt_version; /* supported UPT version */
230 uint64_t upt_features;
231 uint64_t driver_data;
232 uint64_t queue_shared;
233 uint32_t driver_data_len;
234 uint32_t queue_shared_len;
235 uint32_t mtu;
236 uint16_t nrxsg_max;
237 uint8_t ntxqueue;
238 uint8_t nrxqueue;
239 uint32_t reserved1[4];
240
241 /* interrupt control */
242 uint8_t automask;
243 uint8_t nintr;
244 uint8_t evintr;
245 uint8_t modlevel[VMXNET3_MAX_INTRS];
246 uint32_t ictrl;
247 uint32_t reserved2[2];
248
249 /* receive filter parameters */
250 uint32_t rxmode;
251 uint16_t mcast_tablelen;
252 uint16_t pad2;
253 uint64_t mcast_table;
254 uint32_t vlan_filter[4096 / 32];
255
256 struct {
257 uint32_t version;
258 uint32_t len;
259 uint64_t paddr;
260 } rss, pm, plugin;
261
262 uint32_t event;
263 uint32_t reserved3[5];
264} __packed;
265
266struct vmxnet3_txq_shared {
267 uint32_t npending;
268 uint32_t intr_threshold;
269 uint64_t reserved1;
270
271 uint64_t cmd_ring;
272 uint64_t data_ring;
273 uint64_t comp_ring;
274 uint64_t driver_data;
275 uint64_t reserved2;
276 uint32_t cmd_ring_len;
277 uint32_t data_ring_len;
278 uint32_t comp_ring_len;
279 uint32_t driver_data_len;
280 uint8_t intr_idx;
281 uint8_t pad1[7];
282
283 uint8_t stopped;
284 uint8_t pad2[3];
285 uint32_t error;
286
287 struct UPT1_TxStats stats;
288
289 uint8_t pad3[88];
290} __packed;
291
292struct vmxnet3_rxq_shared {
293 uint8_t update_rxhead;
294 uint8_t pad1[7];
295 uint64_t reserved1;
296
297 uint64_t cmd_ring[2];
298 uint64_t comp_ring;
299 uint64_t driver_data;
300 uint64_t reserved2;
301 uint32_t cmd_ring_len[2];
302 uint32_t comp_ring_len;
303 uint32_t driver_data_len;
304 uint8_t intr_idx;
305 uint8_t pad2[7];
306
307 uint8_t stopped;
308 uint8_t pad3[3];
309 uint32_t error;
310
311 struct UPT1_RxStats stats;
312
313 uint8_t pad4[88];
314} __packed;
315
316#define UPT1_RSS_HASH_TYPE_NONE 0x00
317#define UPT1_RSS_HASH_TYPE_IPV4 0x01
318#define UPT1_RSS_HASH_TYPE_TCP_IPV4 0x02
319#define UPT1_RSS_HASH_TYPE_IPV6 0x04
320#define UPT1_RSS_HASH_TYPE_TCP_IPV6 0x08
321
322#define UPT1_RSS_HASH_FUNC_NONE 0x00
323#define UPT1_RSS_HASH_FUNC_TOEPLITZ 0x01
324
325#define UPT1_RSS_MAX_KEY_SIZE 40
326#define UPT1_RSS_MAX_IND_TABLE_SIZE 128
327
328struct vmxnet3_rss_shared {
329 uint16_t hash_type;
330 uint16_t hash_func;
331 uint16_t hash_key_size;
332 uint16_t ind_table_size;
333 uint8_t hash_key[UPT1_RSS_MAX_KEY_SIZE];
334 uint8_t ind_table[UPT1_RSS_MAX_IND_TABLE_SIZE];
335} __packed;
336
337