1/* $NetBSD: intr.h,v 1.60 2019/02/14 08:18:25 cherry Exp $ */
2
3/*-
4 * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum, and by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _X86_INTR_H_
33#define _X86_INTR_H_
34
35#if !defined(XEN)
36#define __HAVE_FAST_SOFTINTS
37#if !defined(NO_PREEMPTION)
38#define __HAVE_PREEMPTION
39#endif /* !defined(NO_PREEMPTION) */
40#endif /* !defined(XEN) */
41
42#ifdef _KERNEL
43#include <sys/types.h>
44#else
45#include <stdbool.h>
46#endif
47
48#include <sys/evcnt.h>
49#include <sys/queue.h>
50#include <machine/intrdefs.h>
51
52#ifndef _LOCORE
53#include <machine/pic.h>
54
55/*
56 * Struct describing an interrupt source for a CPU. struct cpu_info
57 * has an array of MAX_INTR_SOURCES of these. The index in the array
58 * is equal to the stub number of the stubcode as present in vector.s
59 *
60 * The primary CPU's array of interrupt sources has its first 16
61 * entries reserved for legacy ISA irq handlers. This means that
62 * they have a 1:1 mapping for arrayindex:irq_num. This is not
63 * true for interrupts that come in through IO APICs, to find
64 * their source, go through ci->ci_isources[index].is_pic
65 *
66 * It's possible to always maintain a 1:1 mapping, but that means
67 * limiting the total number of interrupt sources to MAX_INTR_SOURCES
68 * (32), instead of 32 per CPU. It also would mean that having multiple
69 * IO APICs which deliver interrupts from an equal pin number would
70 * overlap if they were to be sent to the same CPU.
71 */
72
73struct intrstub {
74 void *ist_entry;
75 void *ist_recurse;
76 void *ist_resume;
77};
78
79struct percpu_evcnt {
80 cpuid_t cpuid;
81 uint64_t count;
82};
83
84struct intrsource {
85 int is_maxlevel; /* max. IPL for this source */
86 int is_pin; /* IRQ for legacy; pin for IO APIC,
87 -1 for MSI */
88 struct intrhand *is_handlers; /* handler chain */
89 struct pic *is_pic; /* originating PIC */
90 void *is_recurse; /* entry for spllower */
91 void *is_resume; /* entry for doreti */
92 lwp_t *is_lwp; /* for soft interrupts */
93#if defined(XEN)
94 u_long ipl_evt_mask1; /* pending events for this IPL */
95 u_long ipl_evt_mask2[NR_EVENT_CHANNELS];
96#endif
97 struct evcnt is_evcnt; /* interrupt counter per cpu */
98 int is_flags; /* see below */
99 int is_type; /* level, edge */
100 int is_idtvec;
101 int is_minlevel;
102 char is_evname[32]; /* event counter name */
103 char is_intrid[INTRIDBUF]; /* intrid created by create_intrid() */
104 char is_xname[INTRDEVNAMEBUF]; /* device names */
105 cpuid_t is_active_cpu; /* active cpuid */
106 struct percpu_evcnt *is_saved_evcnt; /* interrupt count of deactivated cpus */
107 SIMPLEQ_ENTRY(intrsource) is_list; /* link of intrsources */
108};
109
110#define IS_LEGACY 0x0001 /* legacy ISA irq source */
111#define IS_IPI 0x0002
112#define IS_LOG 0x0004
113
114/*
115 * Interrupt handler chains. *_intr_establish() insert a handler into
116 * the list. The handler is called with its (single) argument.
117 */
118
119struct intrhand {
120#if defined(XEN)
121 /*
122 * Note: This is transitional and will go away.
123 * The only current consumer is xen_intr_disestablish()
124 *
125 * We ought to use a union here, but too much effort.
126 * We use this field to tear down the cookie handed to us
127 * via x86/intr.c:intr_disestablish();
128 * Interestingly, the intr_establish_xname() function returns
129 * a "void *" - so we abuse this for now.
130 */
131 int pic_type; /* Overloading wrt struct pintrhand */
132#endif
133 int (*ih_fun)(void *);
134 void *ih_arg;
135 int ih_level;
136 int (*ih_realfun)(void *);
137 void *ih_realarg;
138 struct intrhand *ih_next;
139 struct intrhand **ih_prevp;
140 int ih_pin;
141 int ih_slot;
142#if defined(XEN)
143 struct intrhand *ih_evt_next;
144#endif
145 struct cpu_info *ih_cpu;
146};
147
148#define IMASK(ci,level) (ci)->ci_imask[(level)]
149#define IUNMASK(ci,level) (ci)->ci_iunmask[(level)]
150
151#ifdef _KERNEL
152
153void Xspllower(int);
154void spllower(int);
155int splraise(int);
156void softintr(int);
157
158/*
159 * Convert spl level to local APIC level
160 */
161
162#define APIC_LEVEL(l) ((l) << 4)
163
164/*
165 * Miscellaneous
166 */
167
168#define SPL_ASSERT_BELOW(x) KDASSERT(curcpu()->ci_ilevel < (x))
169#define spl0() spllower(IPL_NONE)
170#define splx(x) spllower(x)
171
172typedef uint8_t ipl_t;
173typedef struct {
174 ipl_t _ipl;
175} ipl_cookie_t;
176
177static inline ipl_cookie_t
178makeiplcookie(ipl_t ipl)
179{
180
181 return (ipl_cookie_t){._ipl = ipl};
182}
183
184static inline int
185splraiseipl(ipl_cookie_t icookie)
186{
187
188 return splraise(icookie._ipl);
189}
190
191#include <sys/spl.h>
192
193/*
194 * Stub declarations.
195 */
196
197void Xsoftintr(void);
198void Xrecurse_preempt(void);
199void Xresume_preempt(void);
200
201extern struct intrstub legacy_stubs[];
202extern struct intrstub ioapic_edge_stubs[];
203extern struct intrstub ioapic_level_stubs[];
204extern struct intrstub x2apic_edge_stubs[];
205extern struct intrstub x2apic_level_stubs[];
206
207struct cpu_info;
208
209struct pcibus_attach_args;
210
211typedef uint64_t intr_handle_t;
212
213void intr_default_setup(void);
214void x86_nmi(void);
215void *intr_establish_xname(int, struct pic *, int, int, int, int (*)(void *),
216 void *, bool, const char *);
217void *intr_establish(int, struct pic *, int, int, int, int (*)(void *), void *, bool);
218void intr_disestablish(struct intrhand *);
219void intr_add_pcibus(struct pcibus_attach_args *);
220const char *intr_string(intr_handle_t, char *, size_t);
221void cpu_intr_init(struct cpu_info *);
222int intr_find_mpmapping(int, int, intr_handle_t *);
223struct pic *intr_findpic(int);
224void intr_printconfig(void);
225
226const char *intr_create_intrid(int, struct pic *, int, char *, size_t);
227struct intrsource *intr_allocate_io_intrsource(const char *);
228void intr_free_io_intrsource(const char *);
229
230int x86_send_ipi(struct cpu_info *, int);
231void x86_broadcast_ipi(int);
232void x86_ipi_handler(void);
233
234#ifndef XENPV
235extern void (* const ipifunc[X86_NIPI])(struct cpu_info *);
236#endif
237
238#endif /* _KERNEL */
239
240#endif /* !_LOCORE */
241
242#endif /* !_X86_INTR_H_ */
243