1/* $NetBSD: i82489reg.h,v 1.19 2019/06/14 05:59:39 msaitoh Exp $ */
2
3/*-
4 * Copyright (c) 1998, 2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Frank van der Linden.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32
33/*
34 * Registers and constants for the 82489DX and Pentium (and up) integrated
35 * "local" APIC.
36 */
37
38#define LAPIC_ID 0x020 /* ID. (xAPIC: RW, x2APIC: RO) */
39# define LAPIC_ID_MASK 0xff000000
40# define LAPIC_ID_SHIFT 24
41
42#define LAPIC_VERS 0x030 /* Version. RO */
43# define LAPIC_VERSION_MASK 0x000000ff
44# define LAPIC_VERSION_LVT_MASK 0x00ff0000
45# define LAPIC_VERSION_LVT_SHIFT 16
46# define LAPIC_VERSION_DIRECTED_EOI 0x01000000
47# define LAPIC_VERSION_EXTAPIC_SPACE 0x80000000
48
49#define LAPIC_TPRI 0x080 /* Task Prio. RW */
50# define LAPIC_TPRI_MASK 0x000000ff
51# define LAPIC_TPRI_INT_MASK 0x000000f0
52# define LAPIC_TPRI_SUB_MASK 0x0000000f
53
54#define LAPIC_APRI 0x090 /* Arbitration prio (xAPIC: RO, x2APIC: NA) */
55# define LAPIC_APRI_MASK 0x000000ff
56
57#define LAPIC_PPRI 0x0a0 /* Processor prio. RO */
58#define LAPIC_EOI 0x0b0 /* End Int. W */
59#define LAPIC_RRR 0x0c0 /* Remote read (xAPIC: RO, x2APIC: NA) */
60#define LAPIC_LDR 0x0d0 /* Logical dest. (xAPIC: RW, x2APIC: RO) */
61
62#define LAPIC_DFR 0x0e0 /* Dest. format (xAPIC: RW, x2APIC: NA) */
63# define LAPIC_DFR_MASK 0xf0000000
64# define LAPIC_DFR_FLAT 0xf0000000
65# define LAPIC_DFR_CLUSTER 0x00000000
66
67#define LAPIC_SVR 0x0f0 /* Spurious intvec RW */
68# define LAPIC_SVR_VECTOR_MASK 0x000000ff
69# define LAPIC_SVR_VEC_FIX 0x0000000f
70# define LAPIC_SVR_VEC_PROG 0x000000f0
71# define LAPIC_SVR_ENABLE 0x00000100
72# define LAPIC_SVR_SWEN 0x00000100
73# define LAPIC_SVR_FOCUS 0x00000200
74# define LAPIC_SVR_FDIS 0x00000200
75# define LAPIC_SVR_EOI_BC_DIS 0x00001000
76
77#define LAPIC_ISR 0x100 /* In-Service Status RO */
78#define LAPIC_TMR 0x180 /* Trigger Mode RO */
79#define LAPIC_IRR 0x200 /* Interrupt Req RO */
80#define LAPIC_ESR 0x280 /* Err status. RW */
81
82/* Common definitions for ICR, LVT and MSIDATA */
83#define LAPIC_VECTOR_MASK __BITS(7, 0)
84#define LAPIC_DLMODE_MASK __BITS(10, 8) /* Delivery Mode */
85#define LAPIC_DLMODE_FIXED __SHIFTIN(0, LAPIC_DLMODE_MASK)
86#define LAPIC_DLMODE_LOW __SHIFTIN(1, LAPIC_DLMODE_MASK) /* NA in x2APIC */
87#define LAPIC_DLMODE_SMI __SHIFTIN(2, LAPIC_DLMODE_MASK)
88#define LAPIC_DLMODE_NMI __SHIFTIN(4, LAPIC_DLMODE_MASK)
89#define LAPIC_DLMODE_INIT __SHIFTIN(5, LAPIC_DLMODE_MASK)
90#define LAPIC_DLMODE_STARTUP __SHIFTIN(6, LAPIC_DLMODE_MASK) /* NA in LVT,MSI*/
91#define LAPIC_DLMODE_EXTINT __SHIFTIN(7, LAPIC_DLMODE_MASK) /* NA in x2APIC */
92
93#define LAPIC_DLSTAT_BUSY __BIT(12) /* NA in x2APIC nor MSI */
94#define LAPIC_DLSTAT_IDLE 0x00000000
95
96#define LAPIC_LEVEL_MASK __BIT(14) /* LAPIC_LVT_LINT_RIRR in LVT LINT */
97#define LAPIC_LEVEL_ASSERT LAPIC_LEVEL_MASK
98#define LAPIC_LEVEL_DEASSERT 0x00000000
99
100#define LAPIC_TRIGMODE_MASK __BIT(15)
101#define LAPIC_TRIGMODE_EDGE 0x00000000
102#define LAPIC_TRIGMODE_LEVEL LAPIC_TRIGMODE_MASK
103
104/* Common definitions for LVT */
105#define LAPIC_LVT_MASKED __BIT(16)
106
107#define LAPIC_LVT_CMCI 0x2f0 /* Loc.vec (CMCI) RW */
108#define LAPIC_ICRLO 0x300 /* Int. cmd. (xAPIC: RW, x2APIC: RW64) */
109
110# define LAPIC_DSTMODE_MASK __BIT(11)
111# define LAPIC_DSTMODE_PHYS __SHIFTIN(0, LAPIC_DSTMODE_MASK)
112# define LAPIC_DSTMODE_LOG __SHIFTIN(1, LAPIC_DSTMODE_MASK)
113
114# define LAPIC_DEST_MASK __BITS(19, 18)
115# define LAPIC_DEST_DEFAULT __SHIFTIN(0, LAPIC_DEST_MASK)
116# define LAPIC_DEST_SELF __SHIFTIN(1, LAPIC_DEST_MASK)
117# define LAPIC_DEST_ALLINCL __SHIFTIN(2, LAPIC_DEST_MASK)
118# define LAPIC_DEST_ALLEXCL __SHIFTIN(3, LAPIC_DEST_MASK)
119
120#define LAPIC_ICRHI 0x310 /* Int. cmd. (xAPIC: RW, x2APIC: NA) */
121
122#define LAPIC_LVT_TIMER 0x320 /* Loc.vec.(timer) RW */
123# define LAPIC_LVT_TMM __BITS(18, 17)
124# define LAPIC_LVT_TMM_ONESHOT __SHIFTIN(0, LAPIC_LVT_TMM)
125# define LAPIC_LVT_TMM_PERIODIC __SHIFTIN(1, LAPIC_LVT_TMM)
126# define LAPIC_LVT_TMM_TSCDLT __SHIFTIN(2, LAPIC_LVT_TMM)
127
128#define LAPIC_LVT_THERM 0x330 /* Loc.vec (Thermal) RW */
129#define LAPIC_LVT_PCINT 0x340 /* Loc.vec (Perf Mon) RW */
130#define LAPIC_LVT_LINT0 0x350 /* Loc.vec (LINT0) RW */
131# define LAPIC_LVT_LINT_INP_POL __BIT(13)
132# define LAPIC_LVT_LINT_RIRR __BIT(14)
133
134#define LAPIC_LVT_LINT1 0x360 /* Loc.vec (LINT1) RW */
135#define LAPIC_LVT_ERR 0x370 /* Loc.vec (ERROR) RW */
136#define LAPIC_ICR_TIMER 0x380 /* Initial count RW */
137#define LAPIC_CCR_TIMER 0x390 /* Current count RO */
138
139#define LAPIC_DCR_TIMER 0x3e0 /* Divisor config RW */
140# define LAPIC_DCRT_DIV1 0x0b
141# define LAPIC_DCRT_DIV2 0x00
142# define LAPIC_DCRT_DIV4 0x01
143# define LAPIC_DCRT_DIV8 0x02
144# define LAPIC_DCRT_DIV16 0x03
145# define LAPIC_DCRT_DIV32 0x08
146# define LAPIC_DCRT_DIV64 0x09
147# define LAPIC_DCRT_DIV128 0x0a
148
149#define LAPIC_SELF_IPI 0x3f0 /* SELF IPI (xAPIC: NA, x2APIC: W) */
150# define LAPIC_SELF_IPI_VEC_MASK 0x000000ff
151
152#define LAPIC_MSIADDR_BASE 0xfee00000
153#define LAPIC_MSIADDR_DSTID_MASK __BITS(19, 12)
154#define LAPIC_MSIADDR_RSVD0_MASK __BITS(11, 4)
155#define LAPIC_MSIADDR_RH __BIT(3)
156#define LAPIC_MSIADDR_DM __BIT(2)
157#define LAPIC_MSIADDR_RSVD1_MASK __BITS(1, 0)
158
159#define LAPIC_BASE 0xfee00000
160
161#define LAPIC_IRQ_MASK(i) (1 << ((i) + 1))
162
163/* Extended APIC registers, valid when CPUID features4 EAPIC is present */
164#define LEAPIC_FR 0x400 /* Feature register */
165# define LEAPIC_FR_ELC __BITS(23,16) /* Ext. Lvt Count RO */
166# define LEAPIC_FR_EIDCAP __BIT(2) /* Ext. Apic ID Cap. RO */
167# define LEAPIC_FR_SEIOCAP __BIT(1) /* Specific EOI Cap. RO */
168# define LEAPIC_FR_IERCAP __BIT(0) /* Intr. Enable Reg. RO */
169
170#define LEAPIC_CR 0x410 /* Control Register */
171# define LEAPIC_CR_EID_ENABLE __BIT(2) /* Ext. Apic ID enable */
172# define LEAPIC_CR_SEOI_ENABLE __BIT(1) /* Specific EOI enable */
173# define LEAPIC_CR_IER_ENABLE __BIT(0) /* Enable writes to IER */
174
175#define LEAPIC_SEOIR 0x420 /* Specific EOI Register */
176# define LEAPIC_SEOI_VEC __BITS(7,0)
177
178#define LEAPIC_IER_480 0x480 /* Interrupts 0-31 */
179#define LEAPIC_IER_490 0x490 /* Interrupts 32-63 */
180#define LEAPIC_IER_4B0 0x4B0 /* Interrupts 64-95 */
181#define LEAPIC_IER_4C0 0x4C0 /* Interrupts 96-127 */
182#define LEAPIC_IER_4D0 0x4D0 /* Interrupts 128-159 */
183#define LEAPIC_IER_4E0 0x4E0 /* Interrupts 160-191 */
184#define LEAPIC_IER_4F0 0x4F0 /* Interrupts 192-255 */
185
186/* Extended Local Vector Table Entries */
187#define LEAPIC_LVTR_500 0x500
188#define LEAPIC_LVTR_504 0x504
189#define LEAPIC_LVTR_508 0x508
190#define LEAPIC_LVTR_50C 0x50C
191#define LEAPIC_LVTR_510 0x510
192#define LEAPIC_LVTR_514 0x514
193#define LEAPIC_LVTR_518 0x518
194#define LEAPIC_LVTR_51C 0x51C
195#define LEAPIC_LVTR_520 0x520
196#define LEAPIC_LVTR_524 0x524
197#define LEAPIC_LVTR_528 0x528
198#define LEAPIC_LVTR_52C 0x52C
199#define LEAPIC_LVTR_530 0x530
200# define LEAPIC_LVTR_MASK __BIT(16) /* interrupt masked RW */
201# define LEAPIC_LVTR_DSTAT __BIT(12) /* delivery state RO */
202# define LEAPIC_LVTR_MSGTYPE __BITS(10,8) /* Message type */
203# define LEAPIC_LVTR_VEC __BITS(7,0) /* the intr. vector */
204