1/* $NetBSD: i82093reg.h,v 1.9 2017/11/13 11:45:54 nakayama Exp $ */
2
3#include <x86/i82093reg.h>
4
5#ifdef _KERNEL
6
7#if defined(_KERNEL_OPT)
8#include "opt_multiprocessor.h"
9#endif
10
11#define ioapic_asm_ack(num) \
12 movq _C_LABEL(local_apic_va),%rax ; \
13 movl $0,LAPIC_EOI(%rax)
14
15#define x2apic_asm_ack(num) \
16 movl $(MSR_X2APIC_BASE + MSR_X2APIC_EOI),%ecx ; \
17 xorl %eax,%eax ; \
18 xorl %edx,%edx ; \
19 wrmsr
20
21#ifdef MULTIPROCESSOR
22
23#define ioapic_asm_lock(num) \
24 movb $1,%bl ; \
2576: \
26 xchgb %bl,PIC_LOCK(%rdi) ; \
27 testb %bl,%bl ; \
28 jz 78f ; \
2977: \
30 pause ; \
31 nop ; \
32 nop ; \
33 cmpb $0,PIC_LOCK(%rdi) ; \
34 jne 77b ; \
35 jmp 76b ; \
3678:
37
38#define ioapic_asm_unlock(num) \
39 movb $0,PIC_LOCK(%rdi)
40
41#else
42
43#define ioapic_asm_lock(num)
44#define ioapic_asm_unlock(num)
45
46#endif /* MULTIPROCESSOR */
47
48
49#define ioapic_mask(num) \
50 movq IS_PIC(%r14),%rdi ;\
51 ioapic_asm_lock(num) ;\
52 movl IS_PIN(%r14),%esi ;\
53 leaq 0x10(%rsi,%rsi,1),%rsi ;\
54 movq PIC_IOAPIC(%rdi),%rdi ;\
55 movq IOAPIC_SC_REG(%rdi),%r15 ;\
56 movl %esi, (%r15) ;\
57 movq IOAPIC_SC_DATA(%rdi),%r15 ;\
58 movl (%r15),%esi ;\
59 orl $IOAPIC_REDLO_MASK,%esi ;\
60 andl $~IOAPIC_REDLO_RIRR,%esi ;\
61 movl %esi,(%r15) ;\
62 movq IS_PIC(%r14),%rdi ;\
63 ioapic_asm_unlock(num)
64
65#define ioapic_unmask(num) \
66 cmpq $IREENT_MAGIC,(TF_ERR+8)(%rsp) ;\
67 jne 79f ;\
68 movq IS_PIC(%r14),%rdi ;\
69 ioapic_asm_lock(num) ;\
70 movl IS_PIN(%r14),%esi ;\
71 leaq 0x10(%rsi,%rsi,1),%rsi ;\
72 movq PIC_IOAPIC(%rdi),%rdi ;\
73 movq IOAPIC_SC_REG(%rdi),%r15 ;\
74 movq IOAPIC_SC_DATA(%rdi),%r13 ;\
75 movl %esi, (%r15) ;\
76 movl (%r13),%r12d ;\
77 andl $~(IOAPIC_REDLO_MASK|IOAPIC_REDLO_RIRR),%r12d ;\
78 movl %esi,(%r15) ;\
79 movl %r12d,(%r13) ;\
80 movq IS_PIC(%r14),%rdi ;\
81 ioapic_asm_unlock(num) ;\
8279:
83
84#endif
85